Coping with latency in SOC design

Name: Work Video:
Duration: 3 min 30 s
Description: Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.
Luca P. Carloni; Alberto Sangiovanni‐Vincentelli
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'updated_date': '2024-12-11T14:26:46.042362', 'created_date': '2016-06-24'}
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