Publication Year: 2005
DOI: https://doi.org/10.1109/tcsii.2005.848972
Abstract: Increasing complexity architecture such as on-chip network to overcome limitations of bus of architecture. In this brief, we propose a packet-switched on-chip interconnection a network architecture, through which multiple processing units of different clock system-on-chip frequencies can communicate with each other without global synchronization. The design architecture is analyzed in Show more
Authors:
Publication Year: 2005
DOI: https://doi.org/10.1109/date.2005.33
Abstract: As Moore's ever high-speed implementation. We compare the performance of the arbitration scheme increasing with other known interconnect arbitration schemes. Existing schemes typically focus complex heavily on either low latency of service for some initiators systems-on-chips or on guaranteed bandwidth delivery for other initiators. Our scheme (SoCs), allows service latency Show more
Authors:
Publication Year: 2012
DOI: https://doi.org/10.1088/0034-4885/75/4/046402
Abstract: Enabled by potential have already produced all the high-performance photonic devices required to to realize these types of networks. Through extensive empirical characterization in be much of our work, we demonstrate such feasibility of waveguides, a modulators, switches and photodetectors. We also demonstrate systems that simultaneously key combine many functionalities Show more
Authors:
Publication Year: 1990
DOI: https://doi.org/10.1109/12.53600
Abstract: A performance is presented. The analysis includes both static analysis (i.e. queueing analysis delays are neglected) and queueing analysis. In both cases, the of hierarchical networks are shown to have better cost-benefit ratios. The a queueing analysis is also validated by several simulation experiments. The class impact of two performance Show more
Authors:
Publication Year: 1981
DOI: https://doi.org/10.1109/tc.1981.1675772
Abstract: The binary computations Finally, we analyze the binary tree's capacity to transfer information by between nodes and we compare it to the capacity of a the linear array and the grid. computer. For problems that can be naturally tree divided into a tree structure, a great deal of parallelism is Show more
Authors:
Publication Year: 1988
DOI: https://doi.org/10.1109/31.7600
Abstract: A novel is for VLSI implementation. Cellular neural networks are uniquely suited for proposed. high-speed parallel signal processing.<
Authors:
Publication Year: 2003
DOI: https://doi.org/10.1109/tac.2003.811258
Abstract: We propose class of large-scale nonlinear systems with the strong interconnections. The a NNs are used to approximate the unknown subsystems and interconnections. decentralized Due to the functional approximation capabilities of NNs, the additional neural precautions are not required to be made for avoiding the network possible control singularity problems. Show more
Authors:
Publication Year: 2001
DOI: https://doi.org/10.1145/378239.379048
Abstract: Using on-chip structures design of these networks. the top level wires on a chip and facilitates interconnection modular design. With this approach, system modules (processors, memories, peripherals, networks etc...) communicate by sending packets to one another over the in network. The structured network wiring gives well-controlled electrical parameters that place Show more
Authors:
Publication Year: 2011
DOI: https://doi.org/10.1109/tcad.2011.2157157
Abstract: Photonic technology problems interconnect design. In this paper, we present a methodology for facing characterizing and modeling fundamental photonic building blocks which can subsequently today's be combined to form full photonic network architectures. We also electronic describe a set of tools which can be utilized to chip-scale assess the physical-layer Show more
Authors:
Publication Year: 1982
DOI: DOI not available
Abstract: In the systems with multistage interconnection networks is studied. Four system models paper based on rectangular sw-Banyan with arbitrary fanout are introduced and a four commonly used problem structures such as ring, pipeline, broadcast resource and macropipeline are analyzed. The mapping problem of these structures allocation onto each of the Show more
Authors:
Publication Year: 1981
DOI: https://doi.org/10.1109/c-m.1981.220295
Abstract: Adding buffers in certain system architectures. A word of warning—don't make them to too large. a packet switching network can increase throughput
Authors:
Publication Year: 2006
DOI: https://doi.org/10.1109/tie.2006.881997
Abstract: Renewable energy as grid interconnection. This paper gives an overview of the structures a for the DPGS based on fuel cell, photovoltaic, and wind reliable turbines. In addition, control structures of the grid-side converter are alternative presented, and the possibility of compensation for low-order harmonics is to also discussed. Moreover, Show more
Authors:
Publication Year: 2004
DOI: DOI not available
Abstract: One of systems numerous examples, chapter exercises, and case studies. It incorporates hardware-level is descriptions of concepts, allowing a designer to see all the optimizing steps of the process from abstract design to concrete implementation. ·Case the studies throughout the book draw on extensive author experience in communication designing interconnection networks Show more
Authors:
Publication Year: 2020
DOI: https://doi.org/10.1109/tnse.2020.3038454
Abstract: The heterogeneous Sea information to form the verification chains, while the UAV is (SAGS) dispatched to collect baseline data to verify the data reported networks by MVs, thereby constructing global trust. Then, the hash values significantly of baseline data are delivered to MVs to act as promote calibration baseline data, Show more
Authors:
Publication Year: 2003
DOI: https://doi.org/10.1109/empdp.2002.994207
Abstract: An environment the the parameter delays of a detailed router model to be impact used by SICOSYS can be obtained. that a multiprocessor interconnection subsystem causes on real has application execution time. A general-purpose interconnection network simulator, called SICOSYS, been able to capture essential aspects of the low-level implementation, has Show more
Authors:
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