Title: Synthesis of FPGA Implementations from Loop Algorithms
Abstract: We consider the problem of automatically mapping computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that allows automated generation of FPGA configuration data from a loop nest specified in a high level language. Here, we present a methodology for automatic generation of synthesizable VHDL code specifying a processor array and optimized for FPGA implementation.
Publication Year: 2001
Publication Date: 2001-01-01
Language: en
Type: article
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Cited By Count: 11
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