Title: High-performance implementation of DES algorithm based on FPGA
Abstract: First,the DES algorithm principle is introduced.Second,it’s FPGA implementation based on VHDL is described.Finally the simulation results is presented.In order to improve the traditional DES pipelining design,a novel pipelining method based on sub-key pre-calculated is utilized in this FPGA implementation design.The advantages of the DES system is that the key can be dynamically refreshed,hardware resource consumption is reduced,data processing speed is more improved,the highest clock frequency is up to 222.77MHz,the data rate is up to 14.26Gb/s and is factor 112 times faster than software implementations.Furthermore,the system is a flexible,reliable,reusable,scalable design.
Publication Year: 2009
Publication Date: 2009-01-01
Language: en
Type: article
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