Title: PERFORMANCE ANALYSIS OF VARIOUS MULTIPLIER USING VHDL
Abstract: In early days of Computers, Multiplication was implemented generally with a sequence of addition, subtraction and shift operations. Multiplier modules are common to many DSP applications. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. The various multiplier used are Array, Wallace and Vedic Multiplier. The Razor flip-flop is a timing fault detection technique that employs double sampling by the main and shadow Flip-Flops. Different types of multiplier are going to implement using XILINX ISE Design Suite 14.5 software and the performance will analysed with ordinary multiplier.
Publication Year: 2017
Publication Date: 2017-05-02
Language: en
Type: article
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