Title: High Throughput Vedic Multiplier Using Binary To Excess-1 Code Converter
Abstract: Multipliers is one of the most crucial elements for computation present in speedy arithmetic and logic unit, Multiplier and accumulate unit, microprocessors, DSP's and many more. Since, the throughput of these units is evaluated in terms of the number of multiplication performed per unit time, while meeting the time constraints. Vedic multiplier is one of the most promising solutions as it the fastest and energy efficient as well. This paper proposes a novel 8*8 bit vedic multiplier which is based on urdhvatriyakbhyam sutra and uses Binary to Excess-1 code converter as its key component to increase the speed and reduce the area utilized by the multiplier. We also compare the delay, area and power results of proposed multiplier with existing topology. The proposed multiplier is coded in VHDL. Xillinx ISE 12.4 have been used for synthesis and ISIM for simulation.
Publication Year: 2015
Publication Date: 2015-01-01
Language: en
Type: article
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Cited By Count: 4
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