Title: Design and measurement of a cyclic ADC in 65 nm CMOS
Abstract: This thesis report describes the implementation and measurement results for a cyclic ADC with a programmable resolution between 1 and 15 bits. The ADC is clocked at 10 MHz and converts 1 bit in three clock cycles. Thus for a 10 bit resolution the sampling frequency is 333 kHz. The main requirement is an ENOB better than 9 bits for 10-bit conversions. Measurements of the fabricated chip show an ENOB of 9.4 bits, a DNL of 0.25 LSB and an INL of 0.3 LSB. The power consumption is 6.24 mW and it is fabricated in a 65 nm CMOS process using 0.25 mm2 of silicon area. The ADC is part of an on-chip measurement system used for DC measurements during calibration, verification and test. It is important with a large input voltage range and a low input voltage offset to be able to measure both high and small signals accurately. To meet these requirements a cyclic ADC topology is used, that has an inherent insensitivity to capacitor mismatch and amplifier offset voltages. The operation of the ADC circuit topology is analyzed, the implemented circuit solutions are described and the results from simulations and measurements are reported.
Publication Year: 2015
Publication Date: 2015-01-01
Language: en
Type: article
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