Title: Analysis and Realization of Solution for Fast-locking Frequency Synthesizer
Abstract:The speed of frequency-switching has direct impact on the anti-jamming performance FH communication systems. This paper analyses and simulates the lock time of the PLL frequency synthesizer,and gives ...The speed of frequency-switching has direct impact on the anti-jamming performance FH communication systems. This paper analyses and simulates the lock time of the PLL frequency synthesizer,and gives the solution for various approaches to frequency-switching. By using DDS as divider in PLL,the wide-band frequency-hopping synthesizer in S-band is implemented. The experimental results indicate that the lock time is less than 110 μs with frequency interval of 500 MHz,and with low phase noise and low spurs,the performance of the system is thus enhanced.Read More
Publication Year: 2008
Publication Date: 2008-01-01
Language: en
Type: article
Access and Citation
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot