Publication Information

{'id': 'https://openalex.org/W2138627512', 'doi': 'https://doi.org/10.1109/icemi.2009.5274484', 'title': 'The design of wide BW frequency synthesizer based on the DDS&PLL hybrid method', 'display_name': 'The design of wide BW frequency synthesizer based on the DDS&PLL hybrid method', 'publication_year': 2009, 'publication_date': '2009-08-01', 'ids': {'openalex': 'https://openalex.org/W2138627512', 'doi': 'https://doi.org/10.1109/icemi.2009.5274484', 'mag': '2138627512'}, 'language': 'en', 'primary_location': {'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/icemi.2009.5274484', 'pdf_url': None, 'source': None, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}, 'type': 'article', 'type_crossref': 'proceedings-article', 'indexed_in': ['crossref'], 'open_access': {'is_oa': False, 'oa_status': 'closed', 'oa_url': None, 'any_repository_has_fulltext': False}, 'authorships': [{'author_position': 'first', 'author': {'id': 'https://openalex.org/A5049202383', 'display_name': 'Yongke Li', 'orcid': 'https://orcid.org/0000-0002-9982-9622'}, 'institutions': [{'id': 'https://openalex.org/I4210122191', 'display_name': 'Ordnance Engineering College', 'ror': 'https://ror.org/02mn08y26', 'country_code': 'CN', 'type': 'education', 'lineage': ['https://openalex.org/I4210122191']}], 'countries': ['CN'], 'is_corresponding': True, 'raw_author_name': 'Li YongKe', 'raw_affiliation_strings': ['Department of Optical and Electronic Engineering, Ordnance Engineering College, Shijiazhuang 050003, China'], 'affiliations': [{'raw_affiliation_string': 'Department of Optical and Electronic Engineering, Ordnance Engineering College, Shijiazhuang 050003, China', 'institution_ids': ['https://openalex.org/I4210122191']}]}], 'institution_assertions': [], 'countries_distinct_count': 1, 'institutions_distinct_count': 1, 'corresponding_author_ids': ['https://openalex.org/A5049202383'], 'corresponding_institution_ids': ['https://openalex.org/I4210122191'], 'apc_list': None, 'apc_paid': None, 'fwci': 0.398, 'has_fulltext': True, 'fulltext_origin': 'ngrams', 'cited_by_count': 5, 'citation_normalized_percentile': {'value': 0.652293, 'is_in_top_1_percent': False, 'is_in_top_10_percent': False}, 'cited_by_percentile_year': {'min': 79, 'max': 80}, 'biblio': {'volume': None, 'issue': None, 'first_page': '2', 'last_page': '692'}, 'is_retracted': False, 'is_paratext': False, 'primary_topic': {'id': 'https://openalex.org/T11417', 'display_name': 'Advancements in PLL and VCO Technologies', 'score': 0.9985, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, 'topics': [{'id': 'https://openalex.org/T11417', 'display_name': 'Advancements in PLL and VCO Technologies', 'score': 0.9985, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T12941', 'display_name': 'Embedded Systems and FPGA Design', 'score': 0.9846, 'subfield': {'id': 'https://openalex.org/subfields/2207', 'display_name': 'Control and Systems Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T11447', 'display_name': 'Blind Source Separation Techniques', 'score': 0.9783, 'subfield': {'id': 'https://openalex.org/subfields/1711', 'display_name': 'Signal Processing'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}], 'keywords': [{'id': 'https://openalex.org/keywords/pll-multibit', 'display_name': 'PLL multibit', 'score': 0.7241462}, {'id': 'https://openalex.org/keywords/direct-digital-synthesizer', 'display_name': 'Direct digital synthesizer', 'score': 0.6531023}, {'id': 'https://openalex.org/keywords/dbc', 'display_name': 'dBc', 'score': 0.585188}], 'concepts': [{'id': 'https://openalex.org/C12707504', 'wikidata': 'https://www.wikidata.org/wiki/Q52637', 'display_name': 'Phase-locked loop', 'level': 3, 'score': 0.9368732}, {'id': 'https://openalex.org/C182099602', 'wikidata': 'https://www.wikidata.org/wiki/Q2660678', 'display_name': 'Frequency synthesizer', 'level': 4, 'score': 0.8416585}, {'id': 'https://openalex.org/C77881186', 'wikidata': 'https://www.wikidata.org/wiki/Q7119642', 'display_name': 'PLL multibit', 'level': 4, 'score': 0.7241462}, {'id': 'https://openalex.org/C89631360', 'wikidata': 'https://www.wikidata.org/wiki/Q1428766', 'display_name': 'Phase noise', 'level': 2, 'score': 0.6556681}, {'id': 'https://openalex.org/C166089067', 'wikidata': 'https://www.wikidata.org/wiki/Q1227465', 'display_name': 'Direct digital synthesizer', 'level': 5, 'score': 0.6531023}, {'id': 'https://openalex.org/C193523891', 'wikidata': 'https://www.wikidata.org/wiki/Q1771950', 'display_name': 'dBc', 'level': 3, 'score': 0.585188}, {'id': 'https://openalex.org/C2776257435', 'wikidata': 'https://www.wikidata.org/wiki/Q1576430', 'display_name': 'Bandwidth (computing)', 'level': 2, 'score': 0.5515386}, {'id': 'https://openalex.org/C41008148', 'wikidata': 'https://www.wikidata.org/wiki/Q21198', 'display_name': 'Computer science', 'level': 0, 'score': 0.52693474}, {'id': 'https://openalex.org/C24326235', 'wikidata': 'https://www.wikidata.org/wiki/Q126095', 'display_name': 'Electronic engineering', 'level': 1, 'score': 0.47243863}, {'id': 'https://openalex.org/C25915539', 'wikidata': 'https://www.wikidata.org/wiki/Q220786', 'display_name': 'Automatic frequency control', 'level': 2, 'score': 0.42875046}, {'id': 'https://openalex.org/C127413603', 'wikidata': 'https://www.wikidata.org/wiki/Q11023', 'display_name': 'Engineering', 'level': 0, 'score': 0.2004962}, {'id': 'https://openalex.org/C76155785', 'wikidata': 'https://www.wikidata.org/wiki/Q418', 'display_name': 'Telecommunications', 'level': 1, 'score': 0.19651371}], 'mesh': [], 'locations_count': 1, 'locations': [{'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/icemi.2009.5274484', 'pdf_url': None, 'source': None, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}], 'best_oa_location': None, 'sustainable_development_goals': [{'id': 'https://metadata.un.org/sdg/7', 'display_name': 'Affordable and clean energy', 'score': 0.82}], 'grants': [], 'datasets': [], 'versions': [], 'referenced_works_count': 3, 'referenced_works': ['https://openalex.org/W2134350472', 'https://openalex.org/W2141603529', 'https://openalex.org/W4285719527'], 'related_works': ['https://openalex.org/W3145870900', 'https://openalex.org/W2394106628', 'https://openalex.org/W2393391611', 'https://openalex.org/W2384857702', 'https://openalex.org/W2371350995', 'https://openalex.org/W2371029054', 'https://openalex.org/W2370071821', 'https://openalex.org/W2350996794', 'https://openalex.org/W2162551450', 'https://openalex.org/W2088877925'], 'abstract_inverted_index': {'Frequency': [0, 120], 'synthesizer': [1, 18, 121], 'is': [2], 'an': [3, 26, 123], 'important': [4], 'component': [5], 'in': [6, 19, 48, 55, 70], 'the': [7, 20, 56, 93, 98, 102, 118, 142, 152], 'modem': [8], 'electronic': [9], 'systems.': [10], 'This': [11], 'paper': [12], 'studied': [13], 'a': [14, 59, 132], 'kind': [15], 'of': [16, 104], 'frequency': [17, 40], 'UAV': [21], 'system': [22], 'and': [23, 51, 101, 109, 112, 131, 151], 'put': [24], 'forward': [25], 'improvement': [27, 57], 'method': [28], 'for': [29], 'DDS': [30], '(Direct': [31], 'Digital': [32], 'Synthesis)': [33], '&': [34], 'PLL': [35, 46, 60, 84, 87], '(Phase': [36], 'Locked': [37], 'Loop)': [38], 'hybrid': [39], 'synthesizer.': [41], 'Be': [42], 'further': [43], 'to': [44, 97, 126], 'raise': [45], 'performance': [47, 114], 'fast': [49], 'locking': [50, 99], 'noise': [52], 'immunity': [53], 'ability': [54], 'method,': [58], 'with': [61, 88], 'Analog': [62], 'Adaptive': [63], 'Bandwidth': [64], 'Control': [65], '(AABC)': [66], 'has': [67, 76], 'been': [68, 77], 'designed': [69, 119], 'this': [71], 'paper.': [72], 'The': [73, 86], 'new-type': [74], 'AABC': [75, 89], 'presented': [78], 'based': [79], 'on': [80], 'conventional': [81], 'Charge': [82], 'pump': [83], 'circuit.': [85], 'block': [90], 'can': [91], 'control': [92], 'loop': [94], 'bandwidth': [95], 'according': [96], 'status': [100], 'amount': [103], "inputs'": [105], 'phase': [106, 143], 'error': [107], 'adaptively;': [108], 'consequently': [110], 'low-noise': [111], 'fast-lock': [113], 'are': [115], 'achieved.': [116], 'End,': [117], 'satisfies': [122], '800': [124], 'MHz': [125], '1.8': [127], 'GHz': [128], 'output': [129], 'range': [130], '0.4': [133], 'ms': [134], 'maximum': [135], 'conversion': [136], 'time.': [137], 'Working': [138], 'at': [139, 147], '900': [140], 'MHz,': [141], 'noises': [144], 'are-93': [145], 'dBc/Hz': [146], '200': [148], 'kHz': [149], 'offset,': [150], 'whole': [153], 'circuit': [154], 'draws': [155], '8.7': [156], 'mA': [157], 'current': [158], 'from': [159], '3.0': [160], 'V': [161], 'supply.': [162]}, 'cited_by_api_url': 'https://api.openalex.org/works?filter=cites:W2138627512', 'counts_by_year': [{'year': 2020, 'cited_by_count': 1}, {'year': 2017, 'cited_by_count': 2}, {'year': 2013, 'cited_by_count': 1}], 'updated_date': '2024-12-13T18:21:45.841413', 'created_date': '2016-06-24'}