Title: Implementation of an Efficient Multiplier based on Vedic Mathematics Using High speed adder
Abstract: A high speed controller or processor depends vastly on the multiplier as it is one of the main hardware blocks in most digital signal processing unit as well as in general processors. This paper presents a high speed Vedic multiplier architecture which is quite different from the Conventional Vedic multiplier. The most significant aspect of the proposed method is that, the developed multiplier architecture uses Carry look ahead adder as a key block for fast addition. Using Carry look ahead adder the performance of multiplier is vastly improved. This also gives chances to break whole design into smaller blocks and use it whenever required. So by using structural modeling we can easily make large design by using small design and thus complexity gets reduced for inputs of larger no of bits. We had written code for proposed new Vedic multiplier using VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using XilinxISE8.1i and downloaded to Spartan2 FPGA device. Finally the results are compared with Conventional Vedic multipliers to show the significant improvement in its combinational path delay (speed). The high speed processor requires high speed multipliers and the new Vedic Multiplication technique is very much suitable for this purpose.
Publication Year: 2014
Publication Date: 2014-01-01
Language: en
Type: article
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Cited By Count: 9
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