Title: Implementation of Vedic Multiplier Using Modified Architecture by Routing Rearrangement for High-Optimization
Abstract: For the advancing of modern digital technology standards, there exists a need for the supporting faster, better & optimum digital computational architectures. One of the fastest computational algorithm existing is the Vedic multiplier, which is based on the ancient Indian sutras of Vedic mathematics that perform high-speed calculations with ease, in the existing Vedic multiplier FPGA implementation cannot carry optimization in terms of area occupied, delays and power consumption. This paper proposes a design of modified Vedic multiplier architecture by using add2 modules with different adder configurations for desired performance improvement in terms of LUT’s, delays & power consumption. This is done by a slight rearrangement of routing by modifying the adder architecture modules that are being used in the 4-bit to the 32-bit Vedic multiplier (i.e. 4/8/16/32-bit) to carry out efficient minimization in required fields of the performance measure. The proposed design has been able to achieve an appreciable reduction in delay by a 3.27%, LUT’s by a 0.75-4.39% and power consumption by a 0.39-8.45% when compared to conventional Vedic multiplier design. This proposed design is coded in Verilog and synthesized using EDA tool Xilinx ISE in Vivado design suite v2017.2. The obtained simulated results of the proposed design are analyzed and presented in this paper with the conclusion.
Publication Year: 2018
Publication Date: 2018-10-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 1
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