Title: Presentation and Formal Verification of a Family of Protocols for Latency Insensitive Design
Abstract:With increasing clock frequencies in the gigahertz ranges, the distance signals travel during one clock cycle decreases, making a synchronous clock routing throughout the chip impossible. Therefore, i...With increasing clock frequencies in the gigahertz ranges, the distance signals travel during one clock cycle decreases, making a synchronous clock routing throughout the chip impossible. Therefore, interconnect latency needs to be tolerated, and in IP based design various synchronous logic blocks need to be connected via long interconnects that have communication delays of multiple clock cycles. Sometimes two communicating IPs also belong to different clock domains, making their interaction difficult to implement. Latency insensitive protocols were introduced for cases when the interconnect delay was the main concern but the IPs were under same clock domain. Here we generalize the issue of solving the problem of long interconnects in between IPs for a single-clock domain as well as for a multi-clock domain. We also use a formal verification strategy for making sure that as we gradually refine our protocol, we do not become functionally inequivalent to the original synchronous reference design. Presentation and Formal Verification of a Family of Protocols for Latency Insensitive Design Syed Suhaib, David Berner, Deepak Mathaikutty, Jean-Pierre Talpin, Sandeep Shukla {ssuhaib,damathai,shukla}@vt.edu {david.berner,talpin}@irisa.fr Presentation and Formal Verification of a Family of Protocols for Latency Insensitive Design Syed Suhaib, David Berner, Deepak Mathaikutty, Jean-Pierre Talpin, Sandeep Kumar Shukla Virgina Tech, USA INRIA, France {ssuhaib,damathai,shukla}@vt.edu {dberner,talpin}@irisa.frRead More
Publication Year: 2005
Publication Date: 2005-01-01
Language: en
Type: article
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Cited By Count: 8
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