Title: ECC error correction IP design based on BCH code
Abstract: This paper describes a scheme for the ECC Error Correction IP. The common circuit is extracted based on the traditional BCH (Bose, Ray-Chaudhuri, Hocquenghem) codes innovatively, which make the logic gate requirement reduced by 33%; at the same time, the interleaving idea is used for multi-channel ECC error correction, which can correct 4-bit adjacent errors at most; the p-channel parallel chien search circuit is used to replace the serial search circuit to reduce the error correction delay; the time-sharing error correction makes the reading and writing transparent to ECC error correction process. The simulation and tape show that the design can effectively ensure the correctness of DRAM internal data without affecting its access speed.