Title: Design and analysis of high reliable fault tolerance subsystem for micro computer systems
Abstract: Generally in every communication medium, error correction codes were employed for correcting the obtained errors that are caused in the data due to transmission. The essence of these codes is to add redundant bits using mathematical algorithms at the transmission end and decode the received data to retrieve the original data. This paper presents the design of a Multi bit Error Detection and Correction (MEDC) system which is utilized in the microprocessors along with memory that performs error detection as well as error correction of data which was written and was read from memory using Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes. The proposed MEDC system is synthesized and also simulated through Vivado design suit 2018.3 and was implemented using Kintex-7 FPGA board. Compared with the obtained results with well-known error detection codes, the proposed method is utilized for improving the performance, increase the rate of the error detection and correction in the transmitted data.
Publication Year: 2021
Publication Date: 2021-04-03
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 5
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