Title: A description style for automatic hardware synthesis
Abstract: A behavioural synthesis subset of VHDL is introduced here. This description style does not imply a fixed architecture, is technology independent, is synthesisable, and it is at a level of abstraction which is convenient for the hardware designers. The description style is presented in the form of a template, and for the allowable constructs of this template corresponding hardware structures are defined.
Publication Year: 2014
Publication Date: 2014-08-04
Language: en
Type: article
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