Title: A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC IN 180NM CMOS
Abstract: The primary motivation of the work presented in this paper is to significantlyreduce power consumption in pipelined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables longerbattery life in mobile applications, and lower cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the power dissipation in most high-speed analog to digital conversion applications. This work presents a 9 stage, 10-bit Pipelined ADC with Error Correction Algorithm which achieves the dynamic power consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm CMOS. All the sub-blocks to generate top level Pipelined ADC have been designed in Cadence environmentand simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
Publication Year: 2014
Publication Date: 2014-01-01
Language: en
Type: article
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