Title: A 12-bit 50 MS/s CMOS Pipelined A/D Converter
Abstract: A 12-bit 50 MS/s CMOS pipelined A/D converter(ADC) is presented.This ADC is implemented in the TSMC 0.18 μm 1P6M CMOS process.In this circuit,the traditional sample and hold module is totally removed by taking advantage of the inherent sample and hold function of multiplying DAC(MDAC)to reduce power consumption and distortion.In order to maintain good linearity when input is high frequency signal,this ADC employs time-constant matching techniques.Meanwhile,digital calibration technique helps ADC to be less sensitive to comparator offset.The A/D converter is simulated by Cadence Spectre.The result shows that the converter achieves an SNDR of 72.19 dB and an SFDR of 88.23 dB at Nyquist input.It still maintains an SFDR of 80.51 dB at 50 MHz input.At 50MHz sampling rate,this ADC consumes 128 mW from a 1.8 V supply.
Publication Year: 2011
Publication Date: 2011-01-01
Language: en
Type: article
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