Abstract: The internal architecture of a 2000 MIPS/1000 MFLOPS (peak) high performance low cost CMOS Alpha microprocessor chip is described. This implementation is derived from the Alpha 21164 microprocessor to reduce cost while maintaining high performance. It contains a quad issue superscalar instruction unit, two 64 bit integer execution pipelines, and two 64 bit floating point execution pipelines. The memory unit and bus interface unit have been redesigned to provide a high performance memory system using industry standard PC SRAM and DRAM components.
Publication Year: 2002
Publication Date: 2002-11-22
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 12
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