Title: A Regular Time-Efficient VLSI Architecture for Multiplication Modulo 2~n+1
Abstract: A VLSI architecture is described based on MCSA (Modular Carried Saved Adder) for multiplication modulo a Fermat Prime. The theoretic analysis and the result from synthesis and simulation show that it makes a good trade\|off between speed and area.This modular multiplication makes the IDEA(International Data Encrypt Algorithm) more efficient.
Publication Year: 2000
Publication Date: 2000-01-01
Language: en
Type: article
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