Title: Novel delay-controllable clock buffer and its application
Abstract: The decrease of the timing consistency in design flow at ultra deep submicron(UDSM) induces the invalidation of traditional clock skew scheduling approaches.Aiming at this problem,this work proposed a reconfigurable physical design of clock buffer,e.g.delay controllable clock buffer(DCCB),which could alter its propagation delay according to the corresponding internal reconfiguration on the CMOS connection,the number of steps and the drive strength for each step. Based on the layout static timing analysis,the clock period was optimized by the clock skew scheduling utilizing the DCCB.Experimental results indicate that this approach improves the clock period by approximate 10%~17% higher than the traditional methodologies with the same area and power consumption.
Publication Year: 2008
Publication Date: 2008-01-01
Language: en
Type: article
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