Digital clock manager - AILBRY

Results for 'Digital clock manager' :

Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique

Publication Year: 2009

DOI: https://doi.org/10.1109/tpel.2009.2033066

Abstract:

Authors:
- Majd Ghazi Batarseh
- Wisam Al-Hoor
- L. Huang
- C. Iannello
- Issa Batarseh
Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique

Publication Year: 2008

DOI: https://doi.org/10.1109/pesc.2008.4592415

Abstract:

Authors:
- Majd Ghazi Batarseh
- Wisam Al-Hoor
- Lilly Huang
- Chris Iannello
- Issa Batarseh
A Hybrid True Random Number Generator using Ring Oscillator and Digital Clock Manager

Publication Year: 2021

DOI: https://doi.org/10.1109/icict50816.2021.9358750

Abstract:

Authors:
- Sushant Tupparwar
- N. Mohankumar
Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers

Publication Year: 2010

DOI: https://doi.org/10.1109/fpl.2010.100

Abstract:

Authors:
- Ángel Quirós-Olozábal
- María-Ángeles Cifredo-Chacón
- José-María Guerrero-Rodríguez
Design And Implementation of Digital Clock Manager Based Pseudo-True Random Number Generator

Publication Year: 2022

DOI: https://doi.org/10.1109/gcat55367.2022.9972170

Abstract:

Authors:
- Vishnu Vardhan Gudla
- Vankavala Sri Sai Sita Swapna Jyothi
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/Virtex II-Pro FPGAs: A Case Study of Distributed Power Management

Publication Year: 2010

DOI: DOI not available

Abstract:

Authors:
- Christian Schuck
- Bastian Haetzer
- Jürgen Becker
Using an FPGA digital clock manager to generate sub-nanosecond phase shifts for lidar applications

Publication Year: 2010

DOI: https://doi.org/10.1109/spl.2010.5483021

Abstract:

Authors:
- William J. Gaughan
- Brian Butka
Design of Digital Clock Manager Using Tunable BFD–True Random Number Generator

Publication Year: 2021

DOI: https://doi.org/10.1088/1742-6596/1964/6/062003

Abstract:

Authors:
- A. Chaitanya Krishna
- Ch. Priyanka
- Divya Gampala
Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Publication Year: 2011

DOI: https://doi.org/10.1109/tpel.2011.2173702

Abstract:

Authors:
- D. Navarro
- Óscar Lucía
- L.A. Barragán
- J.I. Artigas
- I. Urriza
- Onofre Sanmartín Jiménez
True Random Number Generator Based on Flip-Flop Resolve Time Instability Boosted by Random Chaotic Source

Publication Year: 2017

DOI: https://doi.org/10.1109/tcsi.2017.2751144

Abstract:

Authors:
- Piotr Z. Wieczorek
- Krzysztof Gołofit
Digital PWM controller for high-frequency low-power DC-DC switching mode power supply

Publication Year: 2009

DOI: https://doi.org/10.1109/ipemc.2009.5157592

Abstract:

Authors:
- Shuibao Guo
- Yanxia Gao
- Yanping Xu
- Xuefang Lin-Shi
- Bruno Allard
Exploitation of Run-TIme Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems

Publication Year: 2007

DOI: DOI not available

Abstract:

Authors:
- Katarina Paulsson
- M. Huebner
- Salih Bayar
- Jürgen Becker
A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers

Publication Year: 2022

DOI: https://doi.org/10.1109/tcsii.2022.3211278

Abstract:

Authors:
- Fabio Frustaci
- Fanny Spagnolo
- Stefania Perri
- Pasquale Corsonello
Random Number Generators Based on Irregular Sampling and Fibonacci–Galois Ring Oscillators

Publication Year: 2019

DOI: https://doi.org/10.1109/tcsii.2019.2933280

Abstract:

Authors:
- Kaya Demir
- Salih Ergün
An Analysis of DCM-Based True Random Number Generator

Publication Year: 2019

DOI: https://doi.org/10.1109/tcsii.2019.2926555

Abstract:

Authors:
- Naoki Fujieda
- Masaaki Takeda
- Shûichi Ichikawa

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Results for 'Digital clock manager' :

Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique

Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique

A Hybrid True Random Number Generator using Ring Oscillator and Digital Clock Manager

Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers

Design And Implementation of Digital Clock Manager Based Pseudo-True Random Number Generator

Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/Virtex II-Pro FPGAs: A Case Study of Distributed Power Management

Using an FPGA digital clock manager to generate sub-nanosecond phase shifts for lidar applications

Design of Digital Clock Manager Using Tunable BFD–True Random Number Generator

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

True Random Number Generator Based on Flip-Flop Resolve Time Instability Boosted by Random Chaotic Source

Digital PWM controller for high-frequency low-power DC-DC switching mode power supply

Exploitation of Run-TIme Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems

A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers

Random Number Generators Based on Irregular Sampling and Fibonacci–Galois Ring Oscillators

An Analysis of DCM-Based True Random Number Generator

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