Title: Processor Modeling and Verification Based on Instruction Set Simulator
Abstract: Instruction Set Simulator(ISS) and its application in processor modeling and verification are introduced. The modeling methods ofInstruction Set Architecture(ISA) and Micro-Architecture(MA) are discussed. Furthermore, the implementation of instruction accurate and cycleaccurate instruction set simulator are also investigated. Multithreading technology is used in integration of debugger with ISS. Application of ISS indevelopment of a cipher specific processor is presented.
Publication Year: 2008
Publication Date: 2008-01-01
Language: en
Type: article
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