Title: PERFORMANCE ENHANCEMENT OF DOUBLE GATE JUNCTIONLESS TRANSISTOR USING HIGH-K SPACER
Abstract: In this paper the impact of varying spacer dielectric on both sides of gate oxide on the device performance of a symmetric double gate Junctionless transistor (DGJNT) is reported. The performance parameter of the device considered in this study are ION/IOFF, DIBL and subthreshold slope. It is observed that there is a significant improvement in ION/IOFF, DIBL and subthreshold slope with spacer dielectric.
Publication Year: 2014
Publication Date: 2014-01-01
Language: en
Type: article
Access and Citation
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot