Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration

Name: Work Video:
Duration: 3 min 30 s
Description: In this paper, a new adaptive PLL is implemented. This PLL employs a simple yet effective jitter test circuit to monitor the PLL jitter performance. Additionally, it uses a digital control unit to dynamically adjust the switched loop filter to suppress the jitter. By using this structure, the trade-off between the PLL locking speed and jitter performance can be balanced
Tian Xia; S. Wyatt; Rupert Ho
{'id': 'https://openalex.org/W2139484866', 'doi': 'https://doi.org/10.1109/dft.2006.26', 'title': 'Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration', 'display_name': 'Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration', 'publication_year': 2006, 'publication_date': '2006-10-01', 'ids': {'openalex': 'https://openalex.org/W2139484866', 'doi': 'https://doi.org/10.1109/dft.2006.26', 'mag': '2139484866'}, 'language': 'en', 'primary_location': {'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/dft.2006.26', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S4210201526', 'display_name': 'Proceedings', 'issn_l': '1550-5774', 'issn': ['1550-5774', '2377-7966'], 'is_oa': False, 'is_in_doaj': False, 'is_core': True, 'host_organization': 'https://openalex.org/P4310319808', 'host_organization_name': 'Institute of Electrical and Electronics Engineers', 'host_organization_lineage': ['https://openalex.org/P4310319808'], 'host_organization_lineage_names': ['Institute of Electrical and Electronics Engineers'], 'type': 'journal'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}, 'type': 'article', 'type_crossref': 'proceedings-article', 'indexed_in': ['crossref'], 'open_access': {'is_oa': False, 'oa_status': 'closed', 'oa_url': None, 'any_repository_has_fulltext': False}, 'authorships': [{'author_position': 'first', 'author': {'id': 'https://openalex.org/A5048747574', 'display_name': 'Tian Xia', 'orcid': 'https://orcid.org/0000-0002-4395-7350'}, 'institutions': [{'id': 'https://openalex.org/I111236770', 'display_name': 'University of Vermont', 'ror': 'https://ror.org/0155zta11', 'country_code': 'US', 'type': 'education', 'lineage': ['https://openalex.org/I111236770']}], 'countries': ['US'], 'is_corresponding': False, 'raw_author_name': 'Tian Xia', 'raw_affiliation_strings': ['University of Vermont, USA,'], 'affiliations': [{'raw_affiliation_string': 'University of Vermont, USA,', 'institution_ids': ['https://openalex.org/I111236770']}]}, {'author_position': 'middle', 'author': {'id': 'https://openalex.org/A5113659042', 'display_name': 'S. Wyatt', 'orcid': None}, 'institutions': [{'id': 'https://openalex.org/I1341412227', 'display_name': 'IBM (United States)', 'ror': 'https://ror.org/05hh8d621', 'country_code': 'US', 'type': 'company', 'lineage': ['https://openalex.org/I1341412227']}], 'countries': ['US'], 'is_corresponding': False, 'raw_author_name': 'Stephen Wyatt', 'raw_affiliation_strings': ['IBM Microelectronics Division, (USA)'], 'affiliations': [{'raw_affiliation_string': 'IBM Microelectronics Division, (USA)', 'institution_ids': ['https://openalex.org/I1341412227']}]}, {'author_position': 'last', 'author': {'id': 'https://openalex.org/A5081850746', 'display_name': 'Rupert Ho', 'orcid': None}, 'institutions': [{'id': 'https://openalex.org/I1341412227', 'display_name': 'IBM (United States)', 'ror': 'https://ror.org/05hh8d621', 'country_code': 'US', 'type': 'company', 'lineage': ['https://openalex.org/I1341412227']}], 'countries': ['US'], 'is_corresponding': False, 'raw_author_name': 'Rupert Ho', 'raw_affiliation_strings': ['IBM Microelectronics Division, (USA)'], 'affiliations': [{'raw_affiliation_string': 'IBM Microelectronics Division, (USA)', 'institution_ids': ['https://openalex.org/I1341412227']}]}], 'institution_assertions': [], 'countries_distinct_count': 1, 'institutions_distinct_count': 2, 'corresponding_author_ids': [], 'corresponding_institution_ids': [], 'apc_list': None, 'apc_paid': None, 'fwci': 0.303, 'has_fulltext': True, 'fulltext_origin': 'ngrams', 'cited_by_count': 1, 'citation_normalized_percentile': {'value': 0.46602, 'is_in_top_1_percent': False, 'is_in_top_10_percent': False}, 'cited_by_percentile_year': {'min': 61, 'max': 68}, 'biblio': {'volume': None, 'issue': None, 'first_page': '12', 'last_page': '19'}, 'is_retracted': False, 'is_paratext': False, 'primary_topic': {'id': 'https://openalex.org/T11417', 'display_name': 'Advancements in PLL and VCO Technologies', 'score': 1.0, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, 'topics': [{'id': 'https://openalex.org/T11417', 'display_name': 'Advancements in PLL and VCO Technologies', 'score': 1.0, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T10323', 'display_name': 'Analog and Mixed-Signal Circuit Design', 'score': 0.9974, 'subfield': {'id': 'https://openalex.org/subfields/2204', 'display_name': 'Biomedical Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T10187', 'display_name': 'Radio Frequency Integrated Circuit Design', 'score': 0.9948, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}], 'keywords': [{'id': 'https://openalex.org/keywords/pll-multibit', 'display_name': 'PLL multibit', 'score': 0.4856726}], 'concepts': [{'id': 'https://openalex.org/C134652429', 'wikidata': 'https://www.wikidata.org/wiki/Q1052698', 'display_name': 'Jitter', 'level': 2, 'score': 0.96860707}, {'id': 'https://openalex.org/C12707504', 'wikidata': 'https://www.wikidata.org/wiki/Q52637', 'display_name': 'Phase-locked loop', 'level': 3, 'score': 0.92373383}, {'id': 'https://openalex.org/C41008148', 'wikidata': 'https://www.wikidata.org/wiki/Q21198', 'display_name': 'Computer science', 'level': 0, 'score': 0.64729935}, {'id': 'https://openalex.org/C184670325', 'wikidata': 'https://www.wikidata.org/wiki/Q512604', 'display_name': 'Loop (graph theory)', 'level': 2, 'score': 0.511876}, {'id': 'https://openalex.org/C77881186', 'wikidata': 'https://www.wikidata.org/wiki/Q7119642', 'display_name': 'PLL multibit', 'level': 4, 'score': 0.4856726}, {'id': 'https://openalex.org/C24326235', 'wikidata': 'https://www.wikidata.org/wiki/Q126095', 'display_name': 'Electronic engineering', 'level': 1, 'score': 0.47904122}, {'id': 'https://openalex.org/C165005293', 'wikidata': 'https://www.wikidata.org/wiki/Q1074500', 'display_name': 'Chip', 'level': 2, 'score': 0.44263884}, {'id': 'https://openalex.org/C47446073', 'wikidata': 'https://www.wikidata.org/wiki/Q5165890', 'display_name': 'Control theory (sociology)', 'level': 3, 'score': 0.3431629}, {'id': 'https://openalex.org/C127413603', 'wikidata': 'https://www.wikidata.org/wiki/Q11023', 'display_name': 'Engineering', 'level': 0, 'score': 0.14774743}, {'id': 'https://openalex.org/C76155785', 'wikidata': 'https://www.wikidata.org/wiki/Q418', 'display_name': 'Telecommunications', 'level': 1, 'score': 0.08924377}, {'id': 'https://openalex.org/C2775924081', 'wikidata': 'https://www.wikidata.org/wiki/Q55608371', 'display_name': 'Control (management)', 'level': 2, 'score': 0.077118665}, {'id': 'https://openalex.org/C33923547', 'wikidata': 'https://www.wikidata.org/wiki/Q395', 'display_name': 'Mathematics', 'level': 0, 'score': 0.0}, {'id': 'https://openalex.org/C114614502', 'wikidata': 'https://www.wikidata.org/wiki/Q76592', 'display_name': 'Combinatorics', 'level': 1, 'score': 0.0}, {'id': 'https://openalex.org/C154945302', 'wikidata': 'https://www.wikidata.org/wiki/Q11660', 'display_name': 'Artificial intelligence', 'level': 1, 'score': 0.0}], 'mesh': [], 'locations_count': 1, 'locations': [{'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/dft.2006.26', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S4210201526', 'display_name': 'Proceedings', 'issn_l': '1550-5774', 'issn': ['1550-5774', '2377-7966'], 'is_oa': False, 'is_in_doaj': False, 'is_core': True, 'host_organization': 'https://openalex.org/P4310319808', 'host_organization_name': 'Institute of Electrical and Electronics Engineers', 'host_organization_lineage': ['https://openalex.org/P4310319808'], 'host_organization_lineage_names': ['Institute of Electrical and Electronics Engineers'], 'type': 'journal'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}], 'best_oa_location': None, 'sustainable_development_goals': [], 'grants': [], 'datasets': [], 'versions': [], 'referenced_works_count': 6, 'referenced_works': ['https://openalex.org/W1691451471', 'https://openalex.org/W2069986603', 'https://openalex.org/W2125896126', 'https://openalex.org/W2142978107', 'https://openalex.org/W2143518412', 'https://openalex.org/W2166809811'], 'related_works': ['https://openalex.org/W984417604', 'https://openalex.org/W3134930219', 'https://openalex.org/W2967785526', 'https://openalex.org/W2498262093', 'https://openalex.org/W2188779191', 'https://openalex.org/W2139484866', 'https://openalex.org/W1994021281', 'https://openalex.org/W188830667', 'https://openalex.org/W1605914315', 'https://openalex.org/W1576949837'], 'abstract_inverted_index': {'In': [0], 'this': [1, 45], 'paper,': [2], 'a': [3, 12, 28], 'new': [4], 'adaptive': [5], 'PLL': [6, 10, 22, 51], 'is': [7], 'implemented.': [8], 'This': [9], 'employs': [11], 'simple': [13], 'yet': [14], 'effective': [15], 'jitter': [16, 23, 55], 'test': [17], 'circuit': [18], 'to': [19, 32, 39], 'monitor': [20], 'the': [21, 35, 41, 47, 50], 'performance.': [24], 'Additionally,': [25], 'it': [26], 'uses': [27], 'digital': [29], 'control': [30], 'unit': [31], 'dynamically': [33], 'adjust': [34], 'switched': [36], 'loop': [37], 'filter': [38], 'suppress': [40], 'jitter.': [42], 'By': [43], 'using': [44], 'structure,': [46], 'trade-off': [48], 'between': [49], 'locking': [52], 'speed': [53], 'and': [54], 'performance': [56], 'can': [57], 'be': [58], 'balanced': [59]}, 'cited_by_api_url': 'https://api.openalex.org/works?filter=cites:W2139484866', 'counts_by_year': [], 'updated_date': '2024-12-08T23:43:53.688240', 'created_date': '2016-06-24'}
Publication Information

Basic Information

Access and Citation

AI Researcher Chatbot

Primary Location

Authors

Topics

Keywords

Related Works
