Publication Information

{'id': 'https://openalex.org/W2120528056', 'doi': 'https://doi.org/10.1109/aspdac.1997.600281', 'title': 'Optimal loop bandwidth design for low noise PLL applications', 'display_name': 'Optimal loop bandwidth design for low noise PLL applications', 'publication_year': 2002, 'publication_date': '2002-11-22', 'ids': {'openalex': 'https://openalex.org/W2120528056', 'doi': 'https://doi.org/10.1109/aspdac.1997.600281', 'mag': '2120528056'}, 'language': 'en', 'primary_location': {'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/aspdac.1997.600281', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S4363608902', 'display_name': 'Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.', 'issn_l': None, 'issn': None, 'is_oa': False, 'is_in_doaj': False, 'is_indexed_in_scopus': False, 'is_core': False, 'host_organization': None, 'host_organization_name': None, 'host_organization_lineage': [], 'host_organization_lineage_names': [], 'type': 'conference'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}, 'type': 'article', 'type_crossref': 'proceedings-article', 'indexed_in': ['crossref'], 'open_access': {'is_oa': False, 'oa_status': 'closed', 'oa_url': None, 'any_repository_has_fulltext': False}, 'authorships': [{'author_position': 'first', 'author': {'id': 'https://openalex.org/A5003683716', 'display_name': 'Kyoohyun Lim', 'orcid': 'https://orcid.org/0000-0003-2655-8718'}, 'institutions': [{'id': 'https://openalex.org/I157485424', 'display_name': 'Korea Advanced Institute of Science and Technology', 'ror': 'https://ror.org/05apxxy63', 'country_code': 'KR', 'type': 'education', 'lineage': ['https://openalex.org/I157485424']}], 'countries': ['KR'], 'is_corresponding': False, 'raw_author_name': 'None Kyoohyun Lim', 'raw_affiliation_strings': ['Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, South Korea'], 'affiliations': [{'raw_affiliation_string': 'Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, South Korea', 'institution_ids': ['https://openalex.org/I157485424']}]}, {'author_position': 'middle', 'author': {'id': 'https://openalex.org/A5100887163', 'display_name': 'Seunghee Choi', 'orcid': None}, 'institutions': [{'id': 'https://openalex.org/I157485424', 'display_name': 'Korea Advanced Institute of Science and Technology', 'ror': 'https://ror.org/05apxxy63', 'country_code': 'KR', 'type': 'education', 'lineage': ['https://openalex.org/I157485424']}], 'countries': ['KR'], 'is_corresponding': False, 'raw_author_name': 'None Seunghee Choi', 'raw_affiliation_strings': ['Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, South Korea'], 'affiliations': [{'raw_affiliation_string': 'Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, South Korea', 'institution_ids': ['https://openalex.org/I157485424']}]}, {'author_position': 'last', 'author': {'id': 'https://openalex.org/A5059615729', 'display_name': 'Beomsup Kim', 'orcid': None}, 'institutions': [{'id': 'https://openalex.org/I142401562', 'display_name': 'Electronics and Telecommunications Research Institute', 'ror': 'https://ror.org/03ysstz10', 'country_code': 'KR', 'type': 'facility', 'lineage': ['https://openalex.org/I142401562']}], 'countries': ['KR'], 'is_corresponding': False, 'raw_author_name': 'None Beomsup Kim', 'raw_affiliation_strings': ['Techno-Economics Department, Electronics and Telecommnications Research Institute, Taejon, South Korea'], 'affiliations': [{'raw_affiliation_string': 'Techno-Economics Department, Electronics and Telecommnications Research Institute, Taejon, South Korea', 'institution_ids': ['https://openalex.org/I142401562']}]}], 'institution_assertions': [], 'countries_distinct_count': 1, 'institutions_distinct_count': 2, 'corresponding_author_ids': [], 'corresponding_institution_ids': [], 'apc_list': None, 'apc_paid': None, 'fwci': 0.656, 'has_fulltext': True, 'fulltext_origin': 'ngrams', 'cited_by_count': 4, 'citation_normalized_percentile': {'value': 0.659691, 'is_in_top_1_percent': False, 'is_in_top_10_percent': False}, 'cited_by_percentile_year': {'min': 71, 'max': 73}, 'biblio': {'volume': 'cas 41', 'issue': None, 'first_page': '425', 'last_page': '428'}, 'is_retracted': False, 'is_paratext': False, 'primary_topic': {'id': 'https://openalex.org/T11417', 'display_name': 'Advancements in PLL and VCO Technologies', 'score': 1.0, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, 'topics': [{'id': 'https://openalex.org/T11417', 'display_name': 'Advancements in PLL and VCO Technologies', 'score': 1.0, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T10323', 'display_name': 'Analog and Mixed-Signal Circuit Design', 'score': 0.9933, 'subfield': {'id': 'https://openalex.org/subfields/2204', 'display_name': 'Biomedical Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T11697', 'display_name': 'Numerical Methods and Algorithms', 'score': 0.9922, 'subfield': {'id': 'https://openalex.org/subfields/1703', 'display_name': 'Computational Theory and Mathematics'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}], 'keywords': [{'id': 'https://openalex.org/keywords/pll-multibit', 'display_name': 'PLL multibit', 'score': 0.8873441}, {'id': 'https://openalex.org/keywords/ring-oscillator', 'display_name': 'Ring oscillator', 'score': 0.48816854}], 'concepts': [{'id': 'https://openalex.org/C134652429', 'wikidata': 'https://www.wikidata.org/wiki/Q1052698', 'display_name': 'Jitter', 'level': 2, 'score': 0.929759}, {'id': 'https://openalex.org/C12707504', 'wikidata': 'https://www.wikidata.org/wiki/Q52637', 'display_name': 'Phase-locked loop', 'level': 3, 'score': 0.91995656}, {'id': 'https://openalex.org/C77881186', 'wikidata': 'https://www.wikidata.org/wiki/Q7119642', 'display_name': 'PLL multibit', 'level': 4, 'score': 0.8873441}, {'id': 'https://openalex.org/C2776257435', 'wikidata': 'https://www.wikidata.org/wiki/Q1576430', 'display_name': 'Bandwidth (computing)', 'level': 2, 'score': 0.71742344}, {'id': 'https://openalex.org/C89631360', 'wikidata': 'https://www.wikidata.org/wiki/Q1428766', 'display_name': 'Phase noise', 'level': 2, 'score': 0.6508104}, {'id': 'https://openalex.org/C41008148', 'wikidata': 'https://www.wikidata.org/wiki/Q21198', 'display_name': 'Computer science', 'level': 0, 'score': 0.5276065}, {'id': 'https://openalex.org/C24326235', 'wikidata': 'https://www.wikidata.org/wiki/Q126095', 'display_name': 'Electronic engineering', 'level': 1, 'score': 0.52450716}, {'id': 'https://openalex.org/C104111718', 'wikidata': 'https://www.wikidata.org/wiki/Q2153973', 'display_name': 'Ring oscillator', 'level': 3, 'score': 0.48816854}, {'id': 'https://openalex.org/C47446073', 'wikidata': 'https://www.wikidata.org/wiki/Q5165890', 'display_name': 'Control theory (sociology)', 'level': 3, 'score': 0.43631428}, {'id': 'https://openalex.org/C127413603', 'wikidata': 'https://www.wikidata.org/wiki/Q11023', 'display_name': 'Engineering', 'level': 0, 'score': 0.26667383}, {'id': 'https://openalex.org/C76155785', 'wikidata': 'https://www.wikidata.org/wiki/Q418', 'display_name': 'Telecommunications', 'level': 1, 'score': 0.15186536}, {'id': 'https://openalex.org/C46362747', 'wikidata': 'https://www.wikidata.org/wiki/Q173431', 'display_name': 'CMOS', 'level': 2, 'score': 0.055429757}, {'id': 'https://openalex.org/C2775924081', 'wikidata': 'https://www.wikidata.org/wiki/Q55608371', 'display_name': 'Control (management)', 'level': 2, 'score': 0.0}, {'id': 'https://openalex.org/C154945302', 'wikidata': 'https://www.wikidata.org/wiki/Q11660', 'display_name': 'Artificial intelligence', 'level': 1, 'score': 0.0}], 'mesh': [], 'locations_count': 1, 'locations': [{'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/aspdac.1997.600281', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S4363608902', 'display_name': 'Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.', 'issn_l': None, 'issn': None, 'is_oa': False, 'is_in_doaj': False, 'is_indexed_in_scopus': False, 'is_core': False, 'host_organization': None, 'host_organization_name': None, 'host_organization_lineage': [], 'host_organization_lineage_names': [], 'type': 'conference'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}], 'best_oa_location': None, 'sustainable_development_goals': [], 'grants': [], 'datasets': [], 'versions': [], 'referenced_works_count': 5, 'referenced_works': ['https://openalex.org/W1513086495', 'https://openalex.org/W1587896736', 'https://openalex.org/W2121087570', 'https://openalex.org/W2153267648', 'https://openalex.org/W2161104767'], 'related_works': ['https://openalex.org/W984417604', 'https://openalex.org/W2566880546', 'https://openalex.org/W2544336511', 'https://openalex.org/W2498262093', 'https://openalex.org/W2474043983', 'https://openalex.org/W2144737022', 'https://openalex.org/W2078513307', 'https://openalex.org/W1994021281', 'https://openalex.org/W1978186604', 'https://openalex.org/W1576949837'], 'abstract_inverted_index': {'This': [0], 'paper': [1], 'presents': [2], 'a': [3, 20, 117], 'salient': [4], 'method': [5], 'to': [6, 58, 104], 'find': [7], 'an': [8, 51, 85], 'optimal': [9, 106], 'bandwidth': [10, 60, 80, 107], 'for': [11, 109], 'low': [12, 110], 'noise': [13, 111], 'phase-locked': [14], 'loop': [15], '(PLL)': [16], 'applications': [17], 'by': [18], 'analyzing': [19], 'discrete-time': [21], 'model': [22, 120], 'of': [23, 38, 61, 71, 81, 93, 98], 'charge-pump': [24], 'PLLs': [25], 'based': [26], 'on': [27, 43, 78], 'ring': [28, 48], 'oscillator': [29, 49], 'VCOs.': [30], 'The': [31, 91], 'analysis': [32, 65, 92], 'shows': [33, 66], 'that': [34, 67], 'the': [35, 39, 44, 47, 59, 62, 68, 72, 79, 94, 102, 105, 124], 'timing': [36, 69, 96], 'jitter': [37, 45, 70, 87, 97], 'PLL': [40, 73, 83, 95, 112, 119], 'system': [41], 'depends': [42, 77], 'in': [46], 'and': [50, 127], 'accumulation': [52], 'factor': [53], 'which': [54], 'is': [55, 89], 'inversely': [56], 'proportional': [57], 'PLL.': [63], 'Further': [64], 'system,': [74], 'however,': [75], 'proportionally': [76], 'tile': [82], 'when': [84], 'external': [86], 'source': [88], 'applied.': [90], 'both': [99], 'cases': [100], 'gives': [101], 'clue': [103], 'design': [108], 'applications.': [113], 'Simulation': [114], 'results': [115], 'using': [116], 'C-language': [118], 'are': [121], 'compared': [122], 'with': [123], 'theoretical': [125], 'predictions': [126], 'show': [128], 'good': [129], 'agreement.': [130]}, 'cited_by_api_url': 'https://api.openalex.org/works?filter=cites:W2120528056', 'counts_by_year': [{'year': 2023, 'cited_by_count': 1}], 'updated_date': '2025-01-19T13:28:04.966744', 'created_date': '2016-06-24'}