Title: Self compensating low noise low power PLL design
Abstract:This paper addresses a new approach for low jitter, low power phase locked loop design. Effects of process-voltage-temperature variation on PLL are studied. A self compensating PLL solution using proc...This paper addresses a new approach for low jitter, low power phase locked loop design. Effects of process-voltage-temperature variation on PLL are studied. A self compensating PLL solution using process-voltage-temperature variation effects compensation method, based on external reference clock signal is presented. The proposed solution shows considerable improvement of frequency stability and power consumption.Read More
Publication Year: 2013
Publication Date: 2013-09-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 1
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