Title: A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs
Abstract:A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventiona...A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.Read More
Publication Year: 2002
Publication Date: 2002-11-19
Language: en
Type: article
Indexed In: ['crossref']
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