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{'id': 'https://openalex.org/W4387024066', 'doi': 'https://doi.org/10.1007/978-3-031-41085-7_2', 'title': 'Basics of Verilog HDL', 'display_name': 'Basics of Verilog HDL', 'publication_year': 2023, 'publication_date': '2023-09-25', 'ids': {'openalex': 'https://openalex.org/W4387024066', 'doi': 'https://doi.org/10.1007/978-3-031-41085-7_2'}, 'language': 'en', 'primary_location': {'is_oa': False, 'landing_page_url': 'https://doi.org/10.1007/978-3-031-41085-7_2', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S4306463937', 'display_name': 'Springer eBooks', 'issn_l': None, 'issn': None, 'is_oa': False, 'is_in_doaj': False, 'is_core': False, 'host_organization': 'https://openalex.org/P4310319965', 'host_organization_name': 'Springer Nature', 'host_organization_lineage': ['https://openalex.org/P4310319965'], 'host_organization_lineage_names': ['Springer Nature'], 'type': 'ebook platform'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}, 'type': 'book-chapter', 'type_crossref': 'book-chapter', 'indexed_in': ['crossref'], 'open_access': {'is_oa': False, 'oa_status': 'closed', 'oa_url': None, 'any_repository_has_fulltext': False}, 'authorships': [{'author_position': 'first', 'author': {'id': 'https://openalex.org/A5032332339', 'display_name': 'Shirshendu Roy', 'orcid': 'https://orcid.org/0000-0001-5274-1036'}, 'institutions': [{'id': 'https://openalex.org/I8977528', 'display_name': 'Dr. Hari Singh Gour University', 'ror': 'https://ror.org/01xapxe37', 'country_code': 'IN', 'type': 'education', 'lineage': ['https://openalex.org/I8977528']}], 'countries': ['IN'], 'is_corresponding': True, 'raw_author_name': 'Shirshendu Roy', 'raw_affiliation_strings': ['Department of Electronics and Communication Engineering, Dayananda Sagar University, Bengaluru, India'], 'affiliations': [{'raw_affiliation_string': 'Department of Electronics and Communication Engineering, Dayananda Sagar University, Bengaluru, India', 'institution_ids': ['https://openalex.org/I8977528']}]}], 'institution_assertions': [], 'countries_distinct_count': 1, 'institutions_distinct_count': 1, 'corresponding_author_ids': ['https://openalex.org/A5032332339'], 'corresponding_institution_ids': ['https://openalex.org/I8977528'], 'apc_list': None, 'apc_paid': None, 'fwci': 0.0, 'has_fulltext': False, 'cited_by_count': 0, 'citation_normalized_percentile': {'value': 0.0, 'is_in_top_1_percent': False, 'is_in_top_10_percent': False}, 'cited_by_percentile_year': {'min': 0, 'max': 71}, 'biblio': {'volume': None, 'issue': None, 'first_page': '15', 'last_page': '38'}, 'is_retracted': False, 'is_paratext': False, 'primary_topic': {'id': 'https://openalex.org/T10904', 'display_name': 'Reconfigurable Computing Systems and Design Methods', 'score': 0.9975, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, 'topics': [{'id': 'https://openalex.org/T10904', 'display_name': 'Reconfigurable Computing Systems and Design Methods', 'score': 0.9975, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T10054', 'display_name': 'Parallel Computing and Performance Optimization', 'score': 0.9894, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T10363', 'display_name': 'Low-Power VLSI Circuit Design and Optimization', 'score': 0.9828, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}], 'keywords': [{'id': 'https://openalex.org/keywords/verilog', 'display_name': 'Verilog', 'score': 0.87447935}, {'id': 'https://openalex.org/keywords/electronic-circuit-design', 'display_name': 'Electronic circuit design', 'score': 0.72849315}, {'id': 'https://openalex.org/keywords/abstraction', 'display_name': 'Abstraction', 'score': 0.7165129}, {'id': 'https://openalex.org/keywords/register-transfer-level', 'display_name': 'Register-transfer level', 'score': 0.539812}, {'id': 'https://openalex.org/keywords/system-level-design', 'display_name': 'System-Level Design', 'score': 0.507116}], 'concepts': [{'id': 'https://openalex.org/C2779030575', 'wikidata': 'https://www.wikidata.org/wiki/Q827773', 'display_name': 'Verilog', 'level': 3, 'score': 0.87447935}, {'id': 'https://openalex.org/C99149447', 'wikidata': 'https://www.wikidata.org/wiki/Q5358339', 'display_name': 'Electronic circuit design', 'level': 3, 'score': 0.72849315}, {'id': 'https://openalex.org/C124304363', 'wikidata': 'https://www.wikidata.org/wiki/Q673661', 'display_name': 'Abstraction', 'level': 2, 'score': 0.7165129}, {'id': 'https://openalex.org/C41008148', 'wikidata': 'https://www.wikidata.org/wiki/Q21198', 'display_name': 'Computer science', 'level': 0, 'score': 0.7104196}, {'id': 'https://openalex.org/C81843906', 'wikidata': 'https://www.wikidata.org/wiki/Q173156', 'display_name': 'Digital electronics', 'level': 3, 'score': 0.60703593}, {'id': 'https://openalex.org/C42143788', 'wikidata': 'https://www.wikidata.org/wiki/Q173341', 'display_name': 'Hardware description language', 'level': 3, 'score': 0.5945747}, {'id': 'https://openalex.org/C134146338', 'wikidata': 'https://www.wikidata.org/wiki/Q1815901', 'display_name': 'Electronic circuit', 'level': 2, 'score': 0.56051695}, {'id': 'https://openalex.org/C34854456', 'wikidata': 'https://www.wikidata.org/wiki/Q1484552', 'display_name': 'Register-transfer level', 'level': 4, 'score': 0.539812}, {'id': 'https://openalex.org/C118524514', 'wikidata': 'https://www.wikidata.org/wiki/Q173212', 'display_name': 'Computer architecture', 'level': 1, 'score': 0.51827043}, {'id': 'https://openalex.org/C9390403', 'wikidata': 'https://www.wikidata.org/wiki/Q3966', 'display_name': 'Computer hardware', 'level': 1, 'score': 0.3724475}, {'id': 'https://openalex.org/C149635348', 'wikidata': 'https://www.wikidata.org/wiki/Q193040', 'display_name': 'Embedded system', 'level': 1, 'score': 0.34970513}, {'id': 'https://openalex.org/C190560348', 'wikidata': 'https://www.wikidata.org/wiki/Q3245116', 'display_name': 'Circuit design', 'level': 2, 'score': 0.25307062}, {'id': 'https://openalex.org/C42935608', 'wikidata': 'https://www.wikidata.org/wiki/Q190411', 'display_name': 'Field-programmable gate array', 'level': 2, 'score': 0.15805975}, {'id': 'https://openalex.org/C127413603', 'wikidata': 'https://www.wikidata.org/wiki/Q11023', 'display_name': 'Engineering', 'level': 0, 'score': 0.12868685}, {'id': 'https://openalex.org/C119599485', 'wikidata': 'https://www.wikidata.org/wiki/Q43035', 'display_name': 'Electrical engineering', 'level': 1, 'score': 0.110974014}, {'id': 'https://openalex.org/C138885662', 'wikidata': 'https://www.wikidata.org/wiki/Q5891', 'display_name': 'Philosophy', 'level': 0, 'score': 0.0}, {'id': 'https://openalex.org/C111472728', 'wikidata': 'https://www.wikidata.org/wiki/Q9471', 'display_name': 'Epistemology', 'level': 1, 'score': 0.0}], 'mesh': [], 'locations_count': 1, 'locations': [{'is_oa': False, 'landing_page_url': 'https://doi.org/10.1007/978-3-031-41085-7_2', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S4306463937', 'display_name': 'Springer eBooks', 'issn_l': None, 'issn': None, 'is_oa': False, 'is_in_doaj': False, 'is_core': False, 'host_organization': 'https://openalex.org/P4310319965', 'host_organization_name': 'Springer Nature', 'host_organization_lineage': ['https://openalex.org/P4310319965'], 'host_organization_lineage_names': ['Springer Nature'], 'type': 'ebook platform'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}], 'best_oa_location': None, 'sustainable_development_goals': [{'score': 0.65, 'display_name': 'Quality education', 'id': 'https://metadata.un.org/sdg/4'}], 'grants': [], 'datasets': [], 'versions': [], 'referenced_works_count': 0, 'referenced_works': [], 'related_works': ['https://openalex.org/W4387024066', 'https://openalex.org/W4233828762', 'https://openalex.org/W2916312349', 'https://openalex.org/W2765967418', 'https://openalex.org/W2389932690', 'https://openalex.org/W2386257256', 'https://openalex.org/W2385740256', 'https://openalex.org/W2366672283', 'https://openalex.org/W2107517480', 'https://openalex.org/W1903717746'], 'abstract_inverted_index': None, 'cited_by_api_url': 'https://api.openalex.org/works?filter=cites:W4387024066', 'counts_by_year': [], 'updated_date': '2024-09-18T00:48:12.206504', 'created_date': '2023-09-26'}