Abstract: Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2/sup n/ + 1. To avoid using (n + 1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2/sup n/ + 1 arithmetic applications. In this paper, for the first time in the open literature, we formally derive modulo 2/sup n/ + 1 squarers that adopt the diminished-1 number system. The resulting implementations are built using only full- or half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly.
Publication Year: 2004
Publication Date: 2004-01-01
Language: en
Type: article
Indexed In: ['crossref']
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