Get quick answers to your questions about the article from our AI researcher chatbot
{'id': 'https://openalex.org/W3195804277', 'doi': None, 'title': 'FPGA-based 16-channel logic analyzer', 'display_name': 'FPGA-based 16-channel logic analyzer', 'publication_year': 2008, 'publication_date': '2008-01-01', 'ids': {'openalex': 'https://openalex.org/W3195804277', 'mag': '3195804277'}, 'language': 'en', 'primary_location': {'is_oa': False, 'landing_page_url': 'https://www.ukdr.uplb.edu.ph/etd-undergrad/2570', 'pdf_url': None, 'source': None, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}, 'type': 'article', 'type_crossref': 'journal-article', 'indexed_in': [], 'open_access': {'is_oa': False, 'oa_status': 'closed', 'oa_url': None, 'any_repository_has_fulltext': False}, 'authorships': [{'author_position': 'first', 'author': {'id': 'https://openalex.org/A5024004355', 'display_name': 'Seroje', 'orcid': None}, 'institutions': [], 'countries': [], 'is_corresponding': True, 'raw_author_name': 'Seroje, , Don Engelbert Recorba', 'raw_affiliation_strings': [], 'affiliations': []}], 'institution_assertions': [], 'countries_distinct_count': 0, 'institutions_distinct_count': 0, 'corresponding_author_ids': ['https://openalex.org/A5024004355'], 'corresponding_institution_ids': [], 'apc_list': None, 'apc_paid': None, 'fwci': 0.0, 'has_fulltext': False, 'cited_by_count': 0, 'citation_normalized_percentile': {'value': 0.0, 'is_in_top_1_percent': False, 'is_in_top_10_percent': False}, 'cited_by_percentile_year': {'min': 0, 'max': 63}, 'biblio': {'volume': None, 'issue': None, 'first_page': None, 'last_page': None}, 'is_retracted': False, 'is_paratext': False, 'primary_topic': {'id': 'https://openalex.org/T10904', 'display_name': 'Reconfigurable Computing Systems and Design Methods', 'score': 0.9503, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, 'topics': [{'id': 'https://openalex.org/T10904', 'display_name': 'Reconfigurable Computing Systems and Design Methods', 'score': 0.9503, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T11417', 'display_name': 'Phase-Locked Loops in High-Speed Circuits', 'score': 0.9361, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T11032', 'display_name': 'Very Large Scale Integration Testing', 'score': 0.9348, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}], 'keywords': [{'id': 'https://openalex.org/keywords/fpga', 'display_name': 'FPGA', 'score': 0.71076}, {'id': 'https://openalex.org/keywords/logic-analyzer', 'display_name': 'Logic analyzer', 'score': 0.6897805}, {'id': 'https://openalex.org/keywords/phase-locked-loops', 'display_name': 'Phase-Locked Loops', 'score': 0.555056}, {'id': 'https://openalex.org/keywords/analog-circuit-fault-diagnosis', 'display_name': 'Analog Circuit Fault Diagnosis', 'score': 0.550416}, {'id': 'https://openalex.org/keywords/high-level-synthesis', 'display_name': 'High-Level Synthesis', 'score': 0.528564}, {'id': 'https://openalex.org/keywords/frequency-synthesizer', 'display_name': 'Frequency Synthesizer', 'score': 0.523288}], 'concepts': [{'id': 'https://openalex.org/C188434589', 'wikidata': 'https://www.wikidata.org/wiki/Q1478762', 'display_name': 'Logic analyzer', 'level': 3, 'score': 0.6897805}, {'id': 'https://openalex.org/C41008148', 'wikidata': 'https://www.wikidata.org/wiki/Q21198', 'display_name': 'Computer science', 'level': 0, 'score': 0.65914655}, {'id': 'https://openalex.org/C42935608', 'wikidata': 'https://www.wikidata.org/wiki/Q190411', 'display_name': 'Field-programmable gate array', 'level': 2, 'score': 0.6029624}, {'id': 'https://openalex.org/C158007255', 'wikidata': 'https://www.wikidata.org/wiki/Q1055222', 'display_name': 'Spectrum analyzer', 'level': 2, 'score': 0.52100825}, {'id': 'https://openalex.org/C127162648', 'wikidata': 'https://www.wikidata.org/wiki/Q16858953', 'display_name': 'Channel (broadcasting)', 'level': 2, 'score': 0.51221937}, {'id': 'https://openalex.org/C9390403', 'wikidata': 'https://www.wikidata.org/wiki/Q3966', 'display_name': 'Computer hardware', 'level': 1, 'score': 0.42765558}, {'id': 'https://openalex.org/C149635348', 'wikidata': 'https://www.wikidata.org/wiki/Q193040', 'display_name': 'Embedded system', 'level': 1, 'score': 0.35897148}, {'id': 'https://openalex.org/C76155785', 'wikidata': 'https://www.wikidata.org/wiki/Q418', 'display_name': 'Telecommunications', 'level': 1, 'score': 0.14302805}], 'mesh': [], 'locations_count': 1, 'locations': [{'is_oa': False, 'landing_page_url': 'https://www.ukdr.uplb.edu.ph/etd-undergrad/2570', 'pdf_url': None, 'source': None, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}], 'best_oa_location': None, 'sustainable_development_goals': [], 'grants': [], 'datasets': [], 'versions': [], 'referenced_works_count': 0, 'referenced_works': [], 'related_works': ['https://openalex.org/W765526420', 'https://openalex.org/W3213001599', 'https://openalex.org/W3182128311', 'https://openalex.org/W2852681005', 'https://openalex.org/W2582844750', 'https://openalex.org/W2532375488', 'https://openalex.org/W2471465889', 'https://openalex.org/W2393897969', 'https://openalex.org/W2383951090', 'https://openalex.org/W2371813566', 'https://openalex.org/W2371200642', 'https://openalex.org/W2369429769', 'https://openalex.org/W2367755838', 'https://openalex.org/W2362267169', 'https://openalex.org/W2356357888', 'https://openalex.org/W2353074228', 'https://openalex.org/W2340487576', 'https://openalex.org/W2311450211', 'https://openalex.org/W2149130205', 'https://openalex.org/W2119033458'], 'abstract_inverted_index': None, 'cited_by_api_url': 'https://api.openalex.org/works?filter=cites:W3195804277', 'counts_by_year': [], 'updated_date': '2024-09-19T01:06:17.747507', 'created_date': '2021-08-30'}