Title: Design and analysis of CMOS based 6T SRAM cell at different technology nodes
Abstract: The CMOS technology is rapidly growing towards large scale integration on a single chip leading to smaller size consuming smaller area. The demand for speed and efficiency are also increasing day by day. With continues down scaling of technologies, the integral density of the chip increases. Stability and reliability of any memory device such as SRAM, DRAM in different environments, is a critical issue. In this paper, the design and analysis of CMOS based 6T SRAM cell at different technology nodes is demonstrated. The main purpose of this paper is to simulate 6T SRAM to evaluate the performance at different CMOS technology nodes (180 nm, 90 nm, 65 nm, 45 nm) with the help of predictive technology model (PTM) file. The constancy of the SRAM bit cell in terms of static noise margin (SNM) is analysed by butterfly curve method. Simulations are done using BSIM3 model PTM files on HSPICE tool. The results shown in this paper clearly indicate that as we proceed from 180 nm to 45 nm delay reduces and stability improves i.e. read static noise margin (RSNM) is improved by 7.72% while write static noise margin (WSNM) is improved by 5.94% of the 6T SRAM cell.
Publication Year: 2020
Publication Date: 2020-01-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 7
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot