Title: Address Alignment and Dynamic Mode Change Based SDRAM Memory Controller
Abstract: Computer system is increasingly limited by memory performance. The gap between processor and external memory increases 50% per year, a dynamic memory controller improves the communication speed between processor and memory. Here scheduling algorithm is presented for synchronous dynamic random access memory (SDRAM). The presented scheme reduces the SDRAM latency by 40%.
Publication Year: 2019
Publication Date: 2019-01-01
Language: en
Type: article
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