Title: 0.8‐V 1.4‐nW multi‐decade frequency range true RMS to DC converter based on two‐quadrant current squarer circuit
Abstract: IET Science, Measurement & TechnologyVolume 14, Issue 1 p. 17-25 Research ArticleFree Access 0.8-V 1.4-nW multi-decade frequency range true RMS to DC converter based on two-quadrant current squarer circuit Mohammad Moradinezhad Maryan, Mohammad Moradinezhad Maryan Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this authorSeyed Javad Azhari, Corresponding Author Seyed Javad Azhari [email protected] Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this authorAhmad Ayatollahi, Ahmad Ayatollahi Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this authorHamed Sajadinia, Hamed Sajadinia Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this author Mohammad Moradinezhad Maryan, Mohammad Moradinezhad Maryan Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this authorSeyed Javad Azhari, Corresponding Author Seyed Javad Azhari [email protected] Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this authorAhmad Ayatollahi, Ahmad Ayatollahi Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this authorHamed Sajadinia, Hamed Sajadinia Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, IranSearch for more papers by this author First published: 01 January 2020 https://doi.org/10.1049/iet-smt.2019.0007Citations: 1AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract A low-voltage ultra-low-power two-quadrant current squarer based-true RMS to DC converter circuit is presented in this study. The proposed current squarer is based on two translinear loops with matched NMOS transistors operating in the weak inversion region. Ultra-low-power dissipation of 1.4 nW, multi-decade frequency range of 0.5 Hz–55 kHz and large input dynamic range of 72 pA–1 nA (with error <3%) are the main achievements of the proposed design while constructed of only ten transistors. Post-layout simulations with 0.8-V supply voltage using HSPICE software in 0.18 μm TSMC CMOS process (level-49 parameters) verified the good functionality of the proposed circuit. Moreover, Monte Carlo analysis is performed to validate the satisfactory PVT robustness and reliability of the design's performance. 1 Introduction The computation of the root-mean-square (RMS) value of a signal, either in voltage or in current, is one of the important tasks in electronic measurement. A true RMS-DC converter circuit, which instantly calculates the RMS value, is an awesome electronic signal processor. It is extensively employed to compute the AC power of electronic equipment and systems such as biomedical, communication and instrumentation ones [1-3]. RMS-to-DC converter circuits have been implemented in bipolar technology [4-8] and modern CMOS technology [9-25]. Current-mode design/processing holds further benefits than voltage-mode one, comprising wider bandwidth, higher linearity, lower power consumption, lower supply voltage and complexity [26, 27]. The current-mode RMS-to-DC converter circuits can also operate in either strong [9-12, 14, 15, 17, 22, 25] or weak [13, 16, 18-21, 23, 24] inversion regions. Those working in weak inversion region usually suffering from low bandwidth, low input dynamic range and low linearity, but their major advantages are low supply voltage and power dissipation. In contrast, the other group in which transistors are biased in the strong inversion region, achieves a wider input range, lower distortion and linearity error, but it needs larger consumed power and supply voltage, therefore not suitable for low-voltage low-power (LV-LP) applications. Depending on the computation method, current-mode RMS-to-DC converters can be grouped into explicit (direct) [16, 19, 22] and implicit (indirect) [11, 13-15, 17, 18, 20, 22-25] types. The explicit computation technique shown in Fig. 1a uses an arrangement of rectifying, squaring, averaging and then square-rooting circuits. This technique utilises more transistors in serial structure, therefore needs larger consumed power and supply voltage. The implicit scheme uses an indirect procedure to accomplish the conversion as is depicted in Fig. 1b while has simpler structure that is favourably independent to bias current, thus benefits from lower supply voltage, power dissipation and chip area. Fig 1Open in figure viewerPowerPoint Block diagram of the current-mode RMS-to-DC converter (a) Explicit scheme, (b) Implicit scheme In this paper, the implicit scheme based-current-mode true RMS-to-DC converter circuit is proposed. The designed circuit consists two main blocks; a two-quadrant current squarer and a low-pass filter circuit. The translinear loops in weak inversion are the vital building cells in the actualisation of the current-mode squarer circuit. Post-layout simulation results with 0.8-V supply voltage show that the total power dissipation is 1.4 nW, in the frequency range of 0.5 Hz–55 kHz and input dynamic range is 72 pA–1 nA (error <3%). The rest of the paper is organised as follows: In Section 2, the proposed current squarer and RMS-to-DC converter circuits are described. The second-order effects are discussed in Section 3. Simulation results, as well as Monte Carlo analysis and comparison, are disclosed in Section 4 and followed by concluding remarks in Section 5. 2 Circuit explanation 2.1 Proposed current-mode squarer/divider Squarer circuits are the vital cells in analogue signal processing that used in communication systems and measurements such as multiplier/dividers, peak amplitude detectors, rectifiers, and RMS-to-DC converters [10-25, 28]. As is depicted in Fig. 2 the proposed current-mode squarer/divider circuit includes six matched NMOS transistors that are based on MOS translinear (MTL) principle and works in the weak inversion region [29]. Exerting the MTL principle to the first loop of M1–M4, results [29] (1) Similarly, the second loop consisting of the M1, M2, M5 and M6, provides (2) Considering the first translinear loop (M1–M4 in Fig. 2) reveals that I1 = I2 = IB and I4 = I3−IIN, so (3) Solving (3) for I3 results (4) Then (4) could be simplified as follows: (5) Equation (5) can be changed to (7) by using power series shown in the following equation: (6) (7) Similar analyses of the second translinear loop (M1, M2, M5 and M6 transistors) in which; I6 = I5 + IIN yields (8) Similarly, using (6) to solve (8) for I5 gives (9) Thus the output current of the proposed block; ISQ becomes: (10) Therefore, (10) obviously implements the two-quadrant current squaring operation of the proposed cell. Fig 2Open in figure viewerPowerPoint Proposed two-quadrant current squarer circuit 2.2 Proposed current-mode true RMS-to-DC converter The transistor-level arrangement of the proposed true RMS to DC converter circuit based on the indirect computation scheme (Fig. 1b) is depicted in Fig. 3. In this circuit first, the 2IB current subtracts from ISQ then pure squaring current ISQ′ inserts into simple log-domain low-pass filter circuit includes capacitor CAVG and transistor Mp1 that is diode-connected. CAVG is the external capacitor that has large value respect to gate-source capacitor of Mp1 to Mp4. This circuit integrates the inserted current thus calculates the average of input signal () as follows: (11) where τ = CAVE/gmp1 is the filter's time constant and gmp1 is the transconductance of the Mp1, and transistors Mp3 and Mp4 have a double aspect ratio than Mp1 transistor. To give a well efficiency for the needed frequency range, the value of capacitor CAVG must be selected such that [18, 24] (12) where IRMS-MAX is the higher end of the output current range, fmin is the lower end of the frequency range, η is sub-threshold exponential slope factor and VT is thermal voltage. Bias and averaging currents (IB = IAVG) are equalised using recurrent path and Mp1–Mp2 simple current mirror. So, from (11) and with attention to Mp4 aspect ratio, it results (13) Equation (13) obviously describes that the output current of the proposed design is the RMS value of the input current. Fig 3Open in figure viewerPowerPoint Transistor-level schematic of the proposed true RMS-to-DC converter circuit 3 Analysis of second-order effects The I–V characteristic of an NMOS transistor that operating in weak inversion is [26, 29] (14) while VDS, VGS, VT and VTH are drain-source, gate-source, thermal and threshold voltages, respectively. Moreover, IS parameter is specific current as follows: (15) Since the error caused by fluctuation of VDS is quite a few, therefore is relinquished and the errors in the proposed RMS to DC converter can be mostly created by the process related mismatches of IDS in ID0 as follows: (16a) (16b) All mismatches can be incorporated in the term (1 + ΔID0)ID0, where ID0 is a mean value and ΔID0 embodies the non-idealities percentage of ID0. So, VGS can be written from (14) as below: (17) Taking currents relation of the first translinear loop of Fig. 2 into account modifies (1)–(18) (18) In which the term λ1 represents the total effective error of the translinear loop of Fig. 2 and is defined as follows: (19) Considering (18) in Fig. 2(20) (21) (22) where λ2 is defined as follows: (23) As a result, for the proposed circuit (24) The ISQ″ current is enforced to filter to be integrated into the time domain. The filter calculates the average of input current signal as follows: (25) Suppose that IB = IAVG′ and with some manipulation, it yields (26) where A and B are defined as (27a) (27b) Comparing (13) and (26) connotes that the second-order effects plus process unconformities totally generate a gain error term. While with good matching and layout drawing (finger technique, symmetric drawing, etc.) of transistors, all λis can accost to one; thus, error terms could be eliminated and make (26) to approach towards (13). Besides, in order to test the mismatch effects, Monte Carlo analysis with 3% variations of the W and L (channel width and length), threshold voltage and gate oxide thickness of all transistors, are also presented in Section 4 that prove well robustness and reliability of the design's performance. 4 Performance evaluation of the proposed RMS-to-DC converter 4.1 Post-layout simulation results The proposed two-quadrant current squarer and RMS-to-DC converter circuits are evaluated using the HSPICE simulator in 0.18 μm TSMC (level-49) CMOS technology. In the simulations, the power supply voltage and RL are set to 0.8-V and 1 kΩ, respectively while CAVG = 100 nF is chosen. The transistors' aspect ratios of the proposed designs are listed in Table 1. Table 1. Transistors aspect ratios of the proposed works Proposed circuits (W/L)1–6 (W/L)p1–2 (W/L)p3–4 current squarer 3.6 μm/0.4 μm — — RMS-to-DC converter 3 μm/0.5 μm 2.5 μm/0.5 μm 5 μm/0.5 μm Fig. 4 demonstrates the DC transfer characteristic of the proposed current squarer/divider, in which the bias current (IB) is 1 nA. The maximum power consumption and linearity error of the DC transfer function are 4.5 nW and 1.8%, respectively. These values show the high linear and very low consumed power suitable for LV-LP applications. Fig 4Open in figure viewerPowerPoint DC transfer characteristic of the proposed two-quadrant current squarer circuit Since the RMS value indicates the AC power of the input signals, it depends on the figure and the amplitude of the signal. The ratio of RMS values to the peak of the signals for sinusoidal, bipolar square, triangular and sawtooth waveforms is computed from (13) to be 1/√2, 1, 1/√3 and 1/√3, respectively [22]. Output characteristics of the proposed true RMS-to-DC converter circuit for sinusoidal, triangular and bipolar square waveforms are depicted in Fig. 5, while the relative errors of (28) for different amplitudes of the corresponding waveforms are illustrated in Fig. 6. (28) It can be seen that the errors <3% are achieved for amplitudes between 72 pA–1 nA, 77 pA–1 nA and 345 pA–1 nA for sinusoidal, triangular and square waveforms, respectively. Simulation results show that the power consumption of the proposed design for the maximum (IIN = 1 nA) and minimum (IIN = 72 pA) accepted input currents is <1.4 nW and 130 pW, while the static (IIN = 0) power dissipation is 82 pW. Implicit scheme based-circuit design that is independent of bias current, plus using MTL principle in weak inversion region and utilisation of only ten transistors are the main reasons for this ultra-low power that makes this circuit most suitable for LV-LP applications. Figs. 7a–d show the steady-state time response of the proposed circuit for 500 pA amplitude and 1 Hz frequency for sinusoidal, triangular, bipolar square and sawtooth waveforms, respectively. The frequency range is one of the most important specifications in electronic processors such as true RMS-to-DC converters. To test the frequency range of the proposed work, increasing and decreasing the frequency of the sinusoidal wave with 600 pA amplitude as an input current signal to RMS value get out of the 3% error. Figs. 8a and b depict the input current signals and corresponding RMS values for the sinusoidal wave with 55 kHz and 0.5 Hz frequency, respectively. It is obvious that the proposed circuit benefits from a multi-decade frequency range. Monte Carlo analysis with 3% variations of the W and L (channel width and length), threshold voltage and gate oxide thickness of all transistors is also performed to confirm the reasonable robustness and reliability of the proposed design's performance [30]. Fig. 9a shows the Monte Carlo analysis of relative error for a sine wave with 1 Hz frequency and 600 pA amplitude, while the mean value is 0.6%. The relative error parameter has also been studied for 3% supply voltage variations and is depicted in Fig. 9b that the mean value is 0.16%. Reliability of the proposed design respect to temperature variation from −25 to 100°C with 25°C steps is also studied. Fig. 10a illustrates the temperature behaviour of the transient response of an input sine wave with 1 Hz frequency and 500 pA amplitude while the relative error is varied from 1.1 to −2.8%. Although the temperature value is widely changed, the acceptable input dynamic range (3% RMSE) is also kept within 410 pA–1.2 nA for worst-case (100°C) as depicted in Fig. 10b. Fig 5Open in figure viewerPowerPoint Characteristics of the proposed RMS-to-DC circuit for sinusoidal, triangular and bipolar square waveforms Fig 6Open in figure viewerPowerPoint Relative errors of the proposed RMS-to-DC circuit for sinusoidal, triangular and bipolar square waveforms Fig 7Open in figure viewerPowerPoint Steady-state time response of the proposed RMS to DC for (a) Sinusoidal, (b) Triangular, (c) Bipolar square, (d) Sawtooth waveforms Fig 8Open in figure viewerPowerPoint Input current signals and RMS values for the sinusoidal wave with (a) 55 kHz, (b) 0.5 Hz frequency Fig 9Open in figure viewerPowerPoint Monte Carlo analysis of relative error value respect to (a) Process variations, (b) Supply voltage variations Fig 10Open in figure viewerPowerPoint Temperature analysis of the proposed circuit (a) Transient response, (b) RMSE Layout arrangement of the proposed current-mode true RMS to DC converter circuit with a chip area of 16.5 × 21 μm2 (without pads) is shown in Fig. 11. In order to ameliorate the layout arrangement, all used transistors are symmetric. Moreover, the total width for some large transistors has been fractured into multiple gate fingers to decrease parasitic resistances and capacitances. Fig 11Open in figure viewerPowerPoint Layout arrangement of the proposed current-mode RMS-to-DC converter circuit 4.2 Proposed RMS-to-DC converter application Biomedical, communication and instrumentation systems are the main applications of the RMS-to-DC converters. However, the proposed design with specific features is the best choice in LV-LP biomedical systems as shown in Fig. 12a. The first stage is the first-order log-domain low-pass filter with the adjustable cut-off frequency which is set to 55 Hz to extract the QRS complex of an electrocardiogram (ECG) signal and reject the unwanted interference signals. The second part is the RMS-to-DC converter to elicit the average energy of the input ECG signal. The conceptual block diagram of the first-order log-domain low-pass filter realisation is depicted in Fig. 12b [24]. The transfer function of an LPF is (29) where K is the DC gain and . Supposing τ = C/g (C and g are capacitance and transconductance values) and the IOUT to be related to a VCAP as follows: (30) IB and α have ampere and 1/volt dimensions, respectively. Equation (29) can be rewritten in time-domain as (31) IB1 and IB2 are constant currents that are able to adjust the cut-off frequency and DC gain of the LPF and are (32) Combining (31) with (32) and rewrite the result (33) Equation (33) demonstrates the transfer function of an LPF (KCL in node A) with DC gain and cut-off frequency of (34) Comparing (30) with (16a) mentions, which if IB = ID0, α = 1/ηVT and VCAP = VGS, the filter output current IOUT of (30) becomes the drain current of a MOS transistor in weak inversion region. In other words, the reported block diagram in Fig. 12b is a log-domain LPF if it satisfies the two conditions; first, (33) is implemented in the structure (node A) and second, the output MOS transistor is operated in a weak inversion region. To have a good performance of the reported LPF the values of the parameters are IB1 = IB2 = 1 nA and C = 100 pF. Fig 12Open in figure viewerPowerPoint Application of the proposed RMS-to-DC converter in biomedical systems (a) Block diagram of ECG signal recording, (b) Conceptual block diagram of the first-order log-domain low-pass filter The treatment of Fig. 12a system has been appraised in the state of real ECG signals obtained from the MIT/BIH database [31]. Fig. 13a shows the ECG signals acquired from MIT/BIH Normal Sinus Rhythm Database (record 16265), while the output RMS value is illustrated in Fig. 13b. Fig 13Open in figure viewerPowerPoint Proposed RMS-to-DC converter performance in biomedical systems (a) Real ECG signal, (b) Output RMS value 4.3 Comparison and discussion A justly and wide comparison between the proposed circuit and other artworks (operating in weak inversion) is stated in Table 2. According to the results, the proposed design concurrently exposure low-voltage operation, smallest power dissipation, large input dynamic range, low distortion, multi-decade frequency range and compact design. Circuit design based on implicit scheme, operation in the weak inversion region and independent design from bias current are the main reasons for its ultra-low power dissipation. The proposed circuit consists of only ten MOS transistors and occupies a very low chip area. To have more evaluation of all these RMS-to-DC converters, three figure of merits (FOMs) are defined as follows: (35) (36) (37) where FOM1 involves dynamic parameters that P is the power dissipation and DR is the input dynamic range. Although, FOM2 contains two static parameters, which N and E are the number of transistors and the relative error of the RMS-to-DC converters, but FOM3 has also been introduced to have a fairly comparison of the frequency range parameter of the reported circuits in which fH and fL are the higher and lower ends of the frequency range, respectively. FOM1 to FOM3 is ordered to show the larger value for the superior circuits. These are calculated and compared for all converters in the table that shows the first-rank superiority of the proposed RMS-to-DC converter. Note that [23] has been reported the static power while other artworks reported the maximum power consumption; therefore FOM1 has been calculated for the proposed circuit with static power equal to 11,625 respect to 7750 of [23]. Moreover FOM3 indicates that the presented work has the widest frequency range with respect to its best counterparts. Table 2. Comparison between the proposed RMS-to-DC circuit and other artworks Ref. Technology, μm Supply voltage, V Power consumption, μW Num. of transistors Frequency range Input dynamic range Bias current FOM1 FOM2 FOM3 [13] 0.35 0.9 <2 μW 7 + 6 FGMOS NAa–650 kHz 0.6–400 nA at 2% NO 200 — — [16] 0.35 1.5 <1 μW 22 NA–5 MHz 0.5–500 nA at 2% 100 pA 500 0.022 — [18] 0.18 1 <3 μW 42 NA–3 MHz 50–500 nA at 3% NO 150 0.008 — [19] 0.18 0.9 <1 μW 32 NA–3.7 MHz 50–500 nA at 3% NO 450 0.01 — [20] 0.18 0.9 <0.9 μW 15 NA 1–400 nA at 4% NO 444.44 0.016 — [21]-a 0.18 0.5 <3.08 nW 165 0.8–75 Hz 80–420 pA at 3% 100 pA 113.3 0.002 19.72 [21]-b 0.18 0.5 <2.6 nW 152 0.9–55 Hz 120–540 pA at 3% 100 pA 161.5 0.002 17.86 [23] 0.35 1.5 >0.12 nWb 20 3–850 Hz 70–1000 pA at 3% 10 pA 7750c 0.016 24.52 [24] 0.18 1 <1 μW 19 0.001–3.6 MHz 60–160 nA at 4% NO 100 0.013 35.56 Proposed 0.18 0.8 0.082–1.4 nW 10 0.5 Hz–55 kHz 72–1000 pA at 3% NO 664.3 (11,625)c 0.033 50.41 aNot Available. bStatic power. cCalculated with static power. 5 Conclusion A CMOS implicit scheme based-true RMS-to-DC converter circuit was proposed in this paper. The designed circuit consists of a two-quadrant current squarer and a low-pass filter circuits. The translinear loops in weak inversion were the basic cells in realisation of the current-mode squarer circuit. Ultra-low-power dissipation, multi-decade frequency range and large input dynamic range were the main achievements of the proposed design. Implicit scheme based-circuit design (independent design of bias current), operation in weak inversion region and utilisation of only ten transistors are the main reasons for this ultra-low-power which makes it most suitable for LV-LP systems such as biomedical applications. Moreover, the presented work has more than five-decade frequency range with respect to its best counterparts. Post-layout simulations using HSPICE software in 0.18 μm TSMC CMOS process verified the functionality and superiority of the proposed circuit. 6 References 1Richman, P.L.: 'A new wideband true RMS-to-DC converter', IEEE Trans. Instrum. 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