Title: Performance Evaluation of Hardware Unit for Fast IP Packet Header Parsing
Abstract: Modern multi-gigabit computer networks are faced with enormous increase of network traffic and constant growth of number of users, servers, connections and demands for new applications, services, and protocols. Assuming that networking devices remain the bottleneck for communication in such networks, the design of fast network processing hardware represents an attractive field of research. Generally, most hardware devices that provide network processing spend a significant part of processor cycles to perform IP packet header field access by means of general-purpose processing. Therefore, this paper proposes a dedicated IP packet header parsing unit that allows direct and single-cycle access to different-sized IP packet header fields with the aim to provide faster network packet processing. The proposed unit is applied to a general-purpose MIPS processor and a memory-centric network processor core and their network processing performances are compared and evaluated. It is shown that the proposed IP header parsing unit speeds-up IP packet headers parsing when applied to both processor cores, leading to multi-gigabit network processing throughput.
Publication Year: 2019
Publication Date: 2019-01-01
Language: en
Type: book-chapter
Indexed In: ['crossref']
Access and Citation
Cited By Count: 1
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