Title: Development of a CAD Tool for the Automatic Generation of Common Analog Layout Structures and Libraries
Abstract: The layout implementation of analog circuits has become a critical part of the design process of integrated circuits (IC). The physical construction of this kind of circuits using transistors with digital characteristics as the only devices available in many nanoscale fabrication technologies is one of the main challenges given the limitations in the transistor’s dimensions, which are constrained to a multiple of the technology’s minimum width and length. In addition to size limitations, analog circuits have to fulfill rigorous design specifications, such as high frequency performance, low noise, and high accuracy, which are strongly dependent on their physical implementation; hence, the optimal layout implementation of the analog circuit becomes of paramount importance in the design process of an integrated circuit. On the other hand, computer-aided design (CAD) tools for analog IC physical design are far from being mature, in contrast to those used for digital IC physical design. Some of the reasons for this are that analog design, in general, is less systematic and more heuristic in nature than digital design. Additionally, analog design often requires specialized knowledge, design skills, and years of experience; analog circuits are more sensitive to parasitic disturbances, EM crosstalk, substrate noise, supply noise, etc.; besides, the variety of schematics and diversity of devices and shapes are much more significant. For all these reasons, the optimal implementation of analog layouts requires several iterations and sometimes rework of the layout, resulting in a very long and expensive developing cycle. In this doctoral dissertation, a novel CAD tool is presented that enables the creation of different layout versions for selected analog structures. The main purpose of the proposed CAD tool is the automatic generation of multiple layout topologies for the subsequent generation of layout libraries or database of two of the most fundamental analog structures: the differential pair and the array of stacked devices. Circuit designers can use this database for the analysis, characterization, optimization, and suitable implementation of their designs. The present doctoral thesis describes several tests and studies for the structures mentioned above, illustrating the functionality and capabilities of the proposed CAD tool for the creation of multiple layout topologies in a very short time, helping designers to reduce the circuit’s design cycle.
Publication Year: 2018
Publication Date: 2018-12-01
Language: en
Type: dissertation
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