Title: Methodology and Tools for Energy-aware Task Mapping on Heterogeneous Multiprocessor Architectures
Abstract: During the last decade, the design of embedded systems was pushed to increase
computational power while maintaining low energy consumption. As an example,
autonomous vehicles such as drones are a representative application domain which
combines vision, wireless communications and other computation intensive kernels
constrained with a limited energy budget. With the advent of Multiprocessor
System-on-Chip (MpSoC) architectures, simplification of processor cores
decreased power consumption per operation, while the multiplication of cores
brought performance improvement. However, the dark silicon issue led to
the benefit of augmenting programmable processors with specialized hardware
accelerators and to the rise of Heterogeneous MpSoC (HMpSoC) combining both
software (SW) and hardware (HW) computational resources. For these heterogeneous
architectures, performance and energy consumption depend on a large set of
parameters such as the HW/SW partitioning, the type of HW implementation or the
communication cost between HW and SW cores therefore leading to a huge design
space.
In this thesis, we study how to reduce the development and implementation
complexity of energy-efficient applications on HMpSoC. Multiple contributions
are proposed to enhance Design Space Exploration (DSE) tools with energy
objectives. First, a formal definition of HMpSoC structure is introduced
alongside with a generic representation focused on the memory hierarchy. Then, a
fast power modelling tool is proposed and validated on several applications.
This power model separates the power sources in three families (static, dynamic
computation and dynamic communication) and computes their contributions on
global consumption independently. With a fine grain communications study, this
approach rapidly computes energy consumption for a given application mapping on
a HMpSoC. In a second time, we propose a methodology for energy-driven
accelerator exploration on HMpSoC. This method builds upon the previous power
model coupled with an Mixed Integer Linear Programming (MILP) formulation and
enables to efficiently select HW accelerators and HW/SW partitioning which
achieve energy efficient-mapping of a tiled application.
The experiments involved in these contributions show the complexity of DSE
validation process on a wide range of applications and architectures. To address
these issues, we introduce a HMpSoC simulator embedding a power model to monitor
application execution. Properties of targeted architectures are described, at
run-time with the previous generic representation model. Furthermore, this
simulator is coupled with an application generator framework that could build an
infinite set of representative applications following predefined computation
models. The obtained applications could then be enriched with mapping directive
and executed on the simulator. This combination enables to ease the research and
validation of new DSE algorithms targeting energy-aware application mapping on a
wide range of HMpSoC architectures.