Title: FPGA Implementation of High Speed Multiplier with Optimized Reduction Phase
Abstract: Multipliers play an important role in DSP applications hence, the delay executed by them is a dominating factor. Various multiplication algorithms are used to enhance the speed of the device. All these multipliers are then compared based on look up table (LUTs) and path delays. The simulated results show that the Wallace tree multiplier is the fastest multiplier, and by using carry look-ahead adder (CLA) for addition, delay is further reduced.
Publication Year: 2018
Publication Date: 2018-01-01
Language: en
Type: book-chapter
Indexed In: ['crossref']
Access and Citation
Cited By Count: 2
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