Title: A New High-Speed Multiplier Based on Carry-Look-Ahead Adder and Compressor
Abstract: This paper presents a new high-speed approximate multiplier using compressor and carry-look-ahead (CLA) adder to increase the speed of the computations. The number of full adders is reduced by introducing compressors. The CLA adder will reduce the waiting time by generating all carry at single instant. Initially, a 4 × 4 multiplier is designed using 4-2 compressor, 5-3 compressor, 5-bit CLA adder, a full adder, and a half adder. Later, the precision of multiplier is increased and designed up to 32 × 32 multiplier. All the designs are extensively simulated and synthesized in the Xilinx ISE 13.1 and targeted to Spartan-6 FPGA (XC6SLX45-CSG324C). The results of proposed approximate multipliers are better compared with exact multipliers in terms of delay. The proposed 32-bit approximate multiplier has a delay of 20.67 ns, which is approximately 5% less than exact multiplier.
Publication Year: 2018
Publication Date: 2018-01-01
Language: en
Type: book-chapter
Indexed In: ['crossref']
Access and Citation
Cited By Count: 10
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot