Title: C142 Investigation of Serious Thermal Resistance in 3D-Integrated Package by Thermal Network Method
Abstract: In the dream chip project of ASET, 3D-integrated chip is developed. The chip has multi layered structure and heat generation density in the chip becomes much larger than conventional single layered chip. Therefore, thermal design of the chip is very important. Since the dream chip is complex structure and there exist so many parameters for thermal design, thermal design with CFD takes long time. In this study, we applied thermal network analysis to the thermal design of the chip and discussed the reduction of the thermal resistance inside the chip.