Title: Engineering a GPS Receiver for Lowest Power Consumption
Abstract: In this work the essential elements of a complete low power GPS receiver targeting portable devices are presented. These building blocks comprise a Low Noise Amplifier (LNA), a radio frequency front-end, a base band processor and a low-level software stack. The achievable reduction in power consumption with respect to currently available solutions is of a factor 3 to 20. After reviewing the challenges faced by a receiver manufacturer planning for the next generation of GPS applications, the TChip approach for low power at both system and device level is presented. The implementation of the single receivers elements is presented, and results based on simulated as well as measured performance are discussed. Lastly, a hardware software co-design platform allowing for fast application prototyping, system-on-a-chip development and real-time receiver characterization is presented.
Publication Year: 2001
Publication Date: 2001-09-14
Language: en
Type: article
Access and Citation
Cited By Count: 1
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot