Title: Evaluating the impact of future memory technologies in the design of multicore processors
Abstract: It’s the Memory, Stupid!
In 1996, Richard Sites, one of the fathers of Computer Architecture and lead designer
of the DEC alpha, wrote a paper [36] with the title above. In that paper he realized that the
only important design issue for microprocessors in the next decade would be the memory
subsystems design.
After more than a decade later, the community of researchers started to digest and
internalize this quote. Now, after more than two decades, it can be said that a lot of progress
has been done since 1996 but the expectations of the enormous data sets that software is
going to handle in the followings years tells that more aggressive designs are needed.
Another reason new memory technologies are needed is because of the multicore architecture
which has increased the required memory bandwidth. This architecture completely
extended across the main computer sectors was the result of continuing the Moore’s law in
exchange of adding more difficulties for software and hardware developers.
All of this has promoted this project. First, it has been decided to create a bridge of
the state of the art DRAM simulator Ramulator [30] with the micro-architecture simulator
TaskSim [34]. Once the bridge has been completed, the second goal of this project has
been to make an evaluation of the impact of the current and future memory technologies in
multicore architectures.
As a first approach, this new infrastructure has been used to evaluate the behavior of
several parallel applications concluding that the execution time of the applications varies
significantly across different memory technologies which even increase the differences while
simulating different processors. The doubtless winner among all the memory technologies
evaluated has been HBM which in some cases has achieved the best expected memory cycle
response time.
Publication Year: 2017
Publication Date: 2017-01-01
Language: en
Type: dissertation
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