Title: Design of GF(2m) multiplier using its subfields
Abstract: A design method of a GF(2m) multiplier using its subfields is presented. This method can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. It has an advantageous feature, namely that a trade-off between hardware complexity and delay time can be achieved.
Publication Year: 1998
Publication Date: 1998-01-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 3
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