Title: A virtual memory architecture to enhance STT-RAM performance as main memory
Abstract: STT-RAM technology is becoming a popular alternative to both SRAM and DRAM. Several studies have proposed to use hybrid or pure STT-RAM architectures as on-chip caches as well as main memory. The main bulk of research targets improving the power consumption of this new memory technology especially due to the power hungry writes. In this paper we present a method to improve the power consumption of STT-RAM when used as a main memory. Our method introduces a novel page replacement policy that can reduce the number of bit write operations and consequently reduce the overall power consumption. This is done by using a simple hashing algorithm to select the target page with the nearest distance. We use a modified 2.6.32.65 Linux kernel, Gem5 full system simulator and a modified NVMain main memory simulator to evaluate the proposed method. Our implementation was able to achieve up to 54% reduction in power consumption compared to STT-RAM implementations of main memory, and 51% power reduction compared to conventional DRAM implementations.
Publication Year: 2016
Publication Date: 2016-05-01
Language: en
Type: article
Indexed In: ['crossref']
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