Title: Fault-Tolerant VLSI Processor Arrays Via Laser Welding'' Arnold L. Rosenberg.
Abstract: We study here a strategy for constructing fault-tolerant VLSI processor arrays that achieves tolerance to faults by running buses past the implemented PEs and configuring the fault-free ones into an array of the desired structure by ``welding'''' PEs into the bank of buses. We build here on earlier studies that have shown this strategy to be competitive in terms of area-efficiency and that have presented and analyzed fault-tolerant ``welded'''' implementations of linear arrays and tree-structured arrays. In this paper, we present and validate a methodology for designing fault-tolerant ``welded'''' implementations of a large variety of families of networks. For a large class of array structures (including, for instance, binary trees, rectangular grids, and cube-connected cycles), the designs produced by the methodology are optimal in area consumption (to within a constant factor) among such ``welded'''' fault-tolerant designs. Moreover, for the ``denser'''' of these arrays (all but the trees), the area of a fault-tolerant ``welded'''' design is just a small constant factor greater than the area of an arbitrary fault-free collinear layout of the array. We illustrate the methodology by deriving ``welded'''' fault-tolerant implementations of tree-structured arrays and rectangular-grid arrays.
Publication Year: 1984
Publication Date: 1984-01-01
Language: en
Type: article
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