Title: On the simulation performance of contemporary AMS hardware description languages
Abstract: Mixed-Signal extensions to VHDL, Verilog, and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of Analog and Mixed Signal (AMS) designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS and SystemC-AMS and compare the simulation performance with HSPICE. The various experimental results observed for the benchmark circuits show the superiority of VHDL-AMS and Verilog-AMS against SystemC-AMS and HSPICE in terms of simulation runtimes at lower level of abstraction.
Publication Year: 2008
Publication Date: 2008-12-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 15
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