Title: Reliability analysis of Safety Logic with Fine Impulse Test system of Indian Prototype Fast Breeder Reactor
Abstract: Safety Logic (SL) System is a safety critical system provided to protect the Prototype Fast Breeder Reactor (PFBR) against various neutronic & thermal incidents. SL system receives trip parameters from various systems such as neutron flux monitoring, failed fuel detection, sodium flow monitoring, reactor inlet temperature monitoring etc and performs logical operations to drive Electro Magnet (EM) coils of Control and Safety Rod Drive Mechanism which holds the absorber rods. Whenever any trip parameter exceeds / falls below the preset threshold or whenever important equipment / system is not available, SL system shuts down the reactor by dropping the absorber rods into the reactor core. The trip parameters are triplicated in nature, i.e. Triple Modular Redundancy (TMR) concept is employed. SL system is built using solid state digital integrated circuits. The EM-Coil drive circuit is built using Insulated Gate Bipolar Transistors (IGBTs). Probable faults in digital integrated circuits are stuck-at 0 or stuck-at 1. For Safety Logic (SL) system, stuck-at 1 is an unsafe condition, which needs to be detected on-line and annunciated in a minimum possible time. To diagnose unsafe faults in SL system, on-line test facility i.e. Fine Impulse Test (FIT) logic is provided. FIT logic injects short duration (1 ms) trip pulses periodically at the input of SL in required combinations and verifies the propagation of these pulses at the output stage of SL system. Whenever any unsafe fault is detected in SL system, the operator is alerted for further action. The digital logic circuits for the Safety Logic with Fine Impulse Test (SLFIT) system have been implemented using Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and targeted to Field Programmable Gate Array (FPGA) devices. The Probability of Failure on Demand (PFD) for SL system shall be <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> /demand. This paper describes the reliability prediction methodology and Failure Mode Effects and Criticality Analysis (FMECA) of SL system.
Publication Year: 2010
Publication Date: 2010-12-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 1
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