Abstract: The access time is important for the system chip with high performance, the low power has been the spotlight and challenge in VLSI design. A 4-Mb CMOS SRAM (512K×8bit)with high speed and low power assumption has been designed in this paper. This SRAM is fabricated in 0.25μm CMOS standard process and employs the traditional six-transistor CMOS memory cell. The reason that influences the access time and power assumption of the memory is analyzed in this paper. The structure, sense amplifier and bit line circuit are emphasized in this paper. The access time of SRAM is 15ns by optimizing the system.
Publication Year: 2005
Publication Date: 2005-01-01
Language: en
Type: article
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