Title: An Experimental Method for High-speed Data Channel Based on FPGA
Abstract: In order to improve the teaching effectiveness of the EDA experiments,a design and experimental simulation method for high-speed data channel based on FPGA was proposed.The high-speed data channel structure which was based on the principle of ping-pong operation used the soft-core dual-clock FIFO provided by Quartus II software to realize flow-through processing of data.The test platform,where FPGA was the data channel between the DSP and the digital up converter AD9857,used the embedded logic analyzer SignalTap II real-time access to data pins to verify the correctness of the design.Under the conditions of reliable communication,the data rate of interface between FPGA and C6416 is 240 MBps and that between FPGA and AD9857 is 22.4 MBps.The design and the experimental method of the system are simple and can be applied to high-speed data streaming applications.
Publication Year: 2012
Publication Date: 2012-01-01
Language: en
Type: article
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