Title: Architecture Design of Simultaneous Multithreading VLIW DSP
Abstract: A novel simultaneous multithreading(SMT) VLIW DSP architecture with dynamic dispatch mechanism was presented.The SMT technology exploits the unused instruction slots by converting the thread-level parallelism to the instruction-level parallelism,improving the efficiency.With the dynamic dispatch mechanism,the processor issues instructions to functional unit at run-time rather than at compile-time,such that the issue conflicts among multiple threads are reduced significantly.The results show that the DSP architecture can effectively increase the functional unit utilization,hide the memory access latency,such that the processor throughput is improved by 26.89% with respect to single thread architecture.
Publication Year: 2010
Publication Date: 2010-01-01
Language: en
Type: article
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