Title: Low power high precision successive approximation register analog to digital converter
Abstract: To achieve high precision,low power dissipation and low cost of dynamic analog-digital converters in modern digital and analog-mixed signal system,a successive approximation register analog-to-digital converter(SAR-ADC) of 10 bits and 200×10~3 samples/s was proposed.The switching sequence of the switched capacitor digital-to-analog converter's capacitor array was optimized,the offset cancellation technique was adopted in the sample-and-hold circuit,and the pre-gain and latch stages were introduced in the comparator design.The chip was fabricated in standard digital complementary metal-oxide-semiconductor process.Testing results show that integral nonlinearity of the converter is less than 1 least-significant-bit(LSB),differential nonlinearity is less than 0.5 LSB.And that signal to noise ratio of 59 dB with 191 Hz input signal and 200 kHz clock frequency is achieved.The power dissipation of the ADC is 2.5 mW at 5 V supply voltage and the die area is about 1.3mm~2.The proposed converter meets the requirements of high linearity and low ADC power dissipation.
Publication Year: 2006
Publication Date: 2006-01-01
Language: en
Type: article
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